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Displaying 1-47 out of 47 total
Special session 12A: Hot topic counterfeit IC identification: How can test help?
Found in: 2013 IEEE 31st VLSI Test Symposium (VTS)
By Ilia Polian,Mohammad Tehranipoor,Ilia Polian,Mohammad Tehranipoor
Issue Date:April 2013
pp. 1
Integrated circuit counterfeiting is a severe challenge for semiconductor companies, system integrators and product end-users. Substantial revenue losses by individual enterprises as well as detrimental economy-wide effects have triggered significant inter...
 
Selective Hardening: Toward Cost-Effective Error Tolerance
Found in: IEEE Design and Test of Computers
By Ilia Polian, John P. Hayes
Issue Date:May 2011
pp. 54-63
<p>As ICs shrink into the nanometer range, they are increasingly subject to errors induced by physical faults. Traditional hardening for error mitigation consumes too much area and energy to be cost-effective in commercial applications. Selective har...
 
Power Droop Testing
Found in: IEEE Design and Test of Computers
By Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker
Issue Date:May 2007
pp. 276-284
Circuit activity is a function of input patterns. When circuit activity changes abruptly, it can cause a sudden drop or rise in power supply voltage. This change is known as power droop and is an instance of power supply noise. Although power droop can cau...
 
Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths
Found in: 2014 27th International Conference on VLSI Design
By Ravi Kanth Uppu,Ravi Tej Uppu,Adit D. Singh,Ilia Polian
Issue Date:January 2014
pp. 133-138
Better-than-worst-case timing designs such as Razor introduce shadow flip-flops triggered by a delayed clock in parallel to the functional flip-flops for timing error detection through duplication and comparision. This arrangement suffers from the "sh...
 
SAT-Based Test Pattern Generation with Improved Dynamic Compaction
Found in: 2014 27th International Conference on VLSI Design
By Alexander Czutro,Sudhakar M. Reddy,Ilia Polian,Bernd Becker
Issue Date:January 2014
pp. 56-61
During the last years, SAT-based ATPG has been proved to be a powerful complement of traditional structural approaches. It outperforms structural methods when applied to hard-to-detect faults, and it can be combined with advanced SAT solving techniques in ...
 
Functional test of small-delay faults using SAT and Craig interpolation
Found in: 2012 IEEE International Test Conference (ITC)
By Matthias Sauer,Stefan Kupferschmid,Alexander Czutro,Ilia Polian,Sudhakar Reddy,Bernd Becker
Issue Date:November 2012
pp. 1-8
We present SATSEQ, a timing-aware ATPG system for small-delay faults in non-scan circuits. The tool identifies the longest paths suitable for functional fault propagation and generates the shortest possible sub-sequences per fault. Based on advanced model-...
 
Session Summary I: Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking
Found in: 2012 21st Asian Test Symposium (ATS)
By Ilia Polian
Issue Date:November 2012
pp. 49
Summary form only given. This special session will introduce the field to the design automation and test community, focusing on recent developments. The ultimate objective of the session is to initiate a dialogue with quantum informatics community by ident...
 
#SAT-based vulnerability analysis of security components — A case study
Found in: 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
By Linus Feiten,Matthias Sauer,Tobias Schubert,Alexander Czutro,Eberhard Bohl,Ilia Polian,Bernd Becker
Issue Date:October 2012
pp. 49-54
In this paper we describe a new approach to assess a circuit's vulnerability to fault attacks. This is achieved through analysis of the circuit's design specification, making use of modern SAT solving techniques. For each injectable fault, a corresponding ...
 
Cross-level protection of circuits against faults and malicious attacks
Found in: 2012 IEEE 18th International On-Line Testing Symposium (IOLTS 2012)
By Victor Tomashevich,Sudarshan Srinivasan,Fabian Foerg,Ilia Polian
Issue Date:June 2012
pp. 150-155
Nanoscale electronics is increasingly affected by disturbances caused by radiation, noise and effects of statistical process variations. Moreover, deliberate injection of faults into cryptographic circuits is used by malicious attackers to perform cryptana...
 
Efficient SAT-Based Search for Longest Sensitisable Paths
Found in: Asian Test Symposium
By Matthias Sauer,Jie Jiang,Alexander Czutro,Ilia Polian,Bernd Becker
Issue Date:November 2011
pp. 108-113
We present a versatile method that enumerates all or a user-specified number of longest sensitisable paths in the whole circuit or through specific components. The path information can be used for design and test of circuits affected by statistical process...
 
Variation-Aware Fault Modeling
Found in: Asian Test Symposium
By Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich
Issue Date:December 2010
pp. 87-93
To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defe...
 
Modeling and Mitigating Transient Errors in Logic Circuits
Found in: IEEE Transactions on Dependable and Secure Computing
By Ilia Polian, John P. Hayes, Sudhakar M. Reddy, Bernd Becker
Issue Date:July 2011
pp. 537-547
Transient or soft errors caused by various environmental effects are a growing concern in micro and nanoelectronics. We present a general framework for modeling and mitigating the logical effects of such errors in digital circuits. We observe that some err...
 
ATPG-based grading of strong fault-secureness
Found in: On-Line Testing Symposium, IEEE International
By Marc Hunger, Sybille Hellebrand, Alejandro Czutro, Ilia Polian, Bernd Becker
Issue Date:June 2009
pp. 269-274
Robust circuit design has become a major concern for nanoscale technologies. As a consequence, for design validation, not only the functionality of a circuit has to be considered, but also its robustness properties have to be analyzed. In this work we prop...
 
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis
Found in: VLSI Design, International Conference on
By Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
Issue Date:January 2009
pp. 227-232
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial ...
 
Selective Hardening of NanoPLA Circuits
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Ilia Polian, Wenjing Rao
Issue Date:October 2008
pp. 263-271
Nanoelectronic components are expected to suffer from very high error rates, implying the need for hardening techniques. We propose a fine-grained approach to harden a promising class of nanoelectronic circuits, called NanoPLAs, against errors. An analytic...
 
On Reducing Circuit Malfunctions Caused by Soft Errors
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, Xun Tang, Bernd Becker
Issue Date:October 2008
pp. 245-253
Soft errors due to radiation are expected to increase in nano?electronic circuits. Methods to reduce system failures due to soft errors include use of redundancy and making circuit elements robust such that soft errors do not upset signal values. Recent wo...
 
A Simulator of Small-Delay Faults Caused by Resistive-Open Defects
Found in: European Test Symposium, IEEE
By Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker
Issue Date:May 2008
pp. 113-118
We present a simulator which determines the coverage of small-delay faults, i.e., delay faults with a size below one clock cycle, caused by resistive-open defects. These defects are likely to escape detection by stuck-at or transition fault patterns. For t...
 
Selective Hardening in Early Design Steps
Found in: European Test Symposium, IEEE
By Christian G. Zoellin, Hans-Joachim Wunderlich, Ilia Polian, Bernd Becker
Issue Date:May 2008
pp. 185-190
Hardening a circuit against soft errors should beperformed in early design steps before the circuit is laid out. Aviable approach to achieve soft error rate (SER) reduction at areasonable cost is to harden only parts of a circuit. When selectingwhich locat...
 
Diagnosis of Realistic Defects Based on the X-Fault Model
Found in: Design and Diagnostics of Electronic Circuits and Systems
By Ilia Polian, Yusuke Nakamura, Piet Engelke, Stefan Spinner, Kohei Miyase, Seiji Kajihara, Bernd Becker, Xiaoqing Wen
Issue Date:April 2008
pp. 1-4
Defects not described by conventional fault models are a challengefor state-of-the-art fault diagnosis techniques. The X-fault model has been introduced recently as a modeling technique for complex defect mechanisms. We analyze the performance of the X-fau...
 
Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Ilia Polian, Sudhakar M. Reddy, Bernd Becker
Issue Date:April 2008
pp. 257-262
Selective hardening aims at achieving maximal soft error rate reduction at reasonable cost by applying hardening techniques to most susceptible circuit nodes only. Logical, electrical and latching-window masking effects must all be considered when calculat...
 
Automatic Test Pattern Generation for Interconnect Open Defects
Found in: VLSI Test Symposium, IEEE
By Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
Issue Date:May 2008
pp. 181-186
We present a fully automated flow to generate test patterns for??interconnect open defects. Both inter-layer opens (open-via defects)??and arbitrary intra-layer opens can be targeted. An aggressor-victim??model used in industry is employed to describe the ...
 
Resistive Bridging Fault Simulation of Industrial Circuits
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Piet Engelke, Ilia Polian, Juergen Schloeffel, Bernd Becker
Issue Date:March 2008
pp. 628-633
We report the successful application of a resistive bridging fault (RBF) simulator to industrial benchmark circuits. Despite the slowdown due to the consideration of the sophisticated RBF model, the run times of the simulator were within an order of magnit...
 
Simulating Open-Via Defects
Found in: Asian Test Symposium
By Stefan Spinner, Jie Jiang, Ilia Polian, Piet Engelke, Bernd Becker
Issue Date:October 2007
pp. 265-270
Open-via defects are a major systematic failure mechanism in nanoscale manufacturing processes. We present a flow for simulating open-via defects. Electrical parameters are extracted from the layout and technology data and represented in a way which allows...
 
An Analysis Framework for Transient-Error Tolerance
Found in: VLSI Test Symposium, IEEE
By John P. Hayes, Ilia Polian, Bernd Becker
Issue Date:May 2007
pp. 249-255
Transient or soft errors are an increasing problem in mainstream microelectronics. We propose a framework for modeling transient-error tolerance (TET) in logic circuits. We classify transient errors as critical or non-critical according to their impact on ...
 
Delta-IDDQ Testing of Resistive Short Defects
Found in: Asian Test Symposium
By Piet Engelke, Ilia Polian, Hans Manhaeve, Michel Renovell, Bernd Becker
Issue Date:November 2006
pp. 63-68
This paper addresses the efficiency of IDDQ and more specifically Delta-IDDQ testing when using a realistic short defect model that properly considers the relation between the resistance of the short and its detectability. The results clearly show that the...
 
Low-Cost Hardening of Image Processing Applications Against Soft Errors
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Ilia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara2
Issue Date:October 2006
pp. 274-279
Image processing systems are increasingly used in safetycritical applications, and their hardening against soft errors becomes an issue. We propose a methodology to identify soft errors as uncritical based on their impact on the system?s functionality. We ...
 
An Improved Technique for Reducing False Alarms Due to Soft Errors
Found in: On-Line Testing Symposium, IEEE International
By Sandip Kundu, Ilia Polian
Issue Date:July 2006
pp. 105-110
A significant fraction of soft errors in modern microprocessors has been reported to never lead to a system failure. Any concurrent error detection scheme that raises alarm every time a soft error is detected will not be well heeded because most of these a...
 
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing
Found in: Asian Test Symposium
By Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker
Issue Date:December 2005
pp. 266-271
Resistive defects are gaining importance in very-deepsubmicron technologies, but their detection conditions are not trivial. Test application can be performed under reduced temperature and/or voltage in order to improve detection of these defects. This is ...
 
A Family of Logical Fault Models for Reversible Circuits
Found in: Asian Test Symposium
By Ilia Polian, Thomas Fiehn, Bernd Becker, John P. Hayes
Issue Date:December 2005
pp. 422-427
Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional circuits such as stuck-at models are not wellsuited to quantum circuits. We d...
 
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies
Found in: VLSI Test Symposium, IEEE
By Ilia Polian, Sandip Kundu, Jean-Marc Galliere, Piet Engelke, Michel Renovell, Bernd Becker
Issue Date:May 2005
pp. 343-348
We present three resistive bridging fault models valid for different CMOS technologies. The models are partitioned into a general framework (which is shared by all three models) and a technology-specific part. The first model is based on Shockley equations...
 
Evolutionary Optimization in Code-Based Test Compression
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Ilia Polian, Alejandro Czutro, Bernd Becker
Issue Date:March 2005
pp. 1124-1129
We provide a general formulation for the code-based test compression problem with fixed-length input blocks and propose a solution approach based on Evolutionary Algorithms. In contrast to existing code-based methods, we allow unspecified values in matchin...
 
Testing for Missing-Gate Faults in Reversible Circuits
Found in: Asian Test Symposium
By John P. Hayes, Ilia Polian, Bernd Becker
Issue Date:November 2004
pp. 100-105
Logical reversibility occurs in low-power applications and is an essential feature of quantum circuits. Of special interest are reversible circuits constructed from a class of reversible elements called k-CNOT (controllable NOT) gates. We review the charac...
 
Automatic Test Pattern Generation for Resistive Bridging Faults
Found in: European Test Symposium, IEEE
By Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
Issue Date:May 2004
pp. 160-165
An ATPG for resistive bridging faults is proposed that combines the advantages of section-based generation and interval-based simulation. In contrast to the solutions introduced so far, it can handle arbitrary non-feedback bridges between two nodes, includ...
 
Simulating Resistive Bridging and Stuck-At Faults
Found in: Test Conference, International
By Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
Issue Date:October 2003
pp. 1051
We present a simulator for resistive bridging and stuck-at faults. In contrast to earlier work, it is based on electrical equations rather than table look-up, thus exposing more flexibility. For the first time, simulation of sequential circuits is dealt wi...
 
Modeling Feedback Bridging Faults With Non-Zero Resistance
Found in: European Test Workshop, IEEE
By Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
Issue Date:May 2003
pp. 91
<p>We study the behavior of feedback bridging faults with non-zero bridge resistance. We demonstrate that a test vector may detect the fault, not detect the fault or lead to oscillation, depending on bridge resistance. Even loops going through a gate...
 
Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Ilia Polian, Bernd Becker, Sudhakar M. Reddy
Issue Date:March 2003
pp. 11184
No summary available.
   
Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests
Found in: Asian Test Symposium
By Ilia Polian, Irith Pomeranz, Bernd Becker
Issue Date:November 2002
pp. 9
n-detection test sets for stuck-at faults have been shown to be useful in detecting unmodeled defects. It was also shown that a set of faults, called maximally dominating faults, can play an important role in controlling the increase in the size of an n-de...
 
Stop & Go BIST
Found in: On-Line Testing Workshop, IEEE International
By Ilia Polian, Bernd Becker
Issue Date:July 2002
pp. 147
A BIST method enabling two-pattern testing at-speed without violating thermal constraints by introducing cool down periods is proposed. The application of the method is demonstrated based on a scalable BIST architecture. Applicability on IP cores is given ...
 
Sequential n -Detection Criteria: Keep It Simple!
Found in: On-Line Testing Workshop, IEEE International
By Ilia Polian, Martin Keim, Nicolai Mallig, Bernd Becker
Issue Date:July 2002
pp. 189
No summary available.
   
Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics
Found in: Multiple-Valued Logic, IEEE International Symposium on
By Ilia Polian, Piet Engelke, Bernd Becker
Issue Date:May 2002
pp. 216
We present the concept of a multi-valued logic simulator for bridging faults in sequential circuits. Different models for the handling of intermediate values in flip-flops on the digital design level can be integrated and result in an Expected realistic be...
 
Fault-based attacks on cryptographic hardware
Found in: 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
By Ilia Polian,Martin Kreuzer
Issue Date:April 2013
pp. 12-17
Mobile and embedded systems increasingly process sensitive data, ranging from personal information including health records or financial transactions to parameters of technical systems such as car engines. Cryptographic circuits are employed to protect the...
   
Tomographic Testing and Validation of Probabilistic Circuits
Found in: European Test Symposium, IEEE
By Alexandru Paler, Armin Alaghi, Ilia Polian, John P. Hayes
Issue Date:May 2011
pp. 63-68
Some emerging technologies for building computers depend on components and signals whose behavior, under normal or fault conditions, is probabilistic. Examples include stochastic and quantum computing circuits, and conventional nano electronic circuits sub...
 
Towards Variation-Aware Test Methods
Found in: European Test Symposium, IEEE
By Ilia Polian, Bernd Becker, Sybille Hellebrand, Hans-Joachim Wunderlich, Peter Maxwell
Issue Date:May 2011
pp. 219-225
Nanoelectronic circuits are increasingly affected by massive statistical process variations, leading to a paradigm shift in both design and test area. In circuit and system design, a broad class of methods for robustness like statistical design and self ca...
 
Small-delay-fault ATPG with waveform accuracy
Found in: Proceedings of the International Conference on Computer-Aided Design (ICCAD '12)
By Alexander Czutro, Bernd Becker, Ilia Polian, Matthias Sauer
Issue Date:November 2012
pp. 30-36
The detection of small-delay faults is traditionally performed by sensitizing transitions on a path of sufficient length from an input to an output of the circuit going through the fault site. While this approach allows efficient test generation algorithms...
     
SUPERB: Simulator utilizing parallel evaluation of resistive bridges
Found in: ACM Transactions on Design Automation of Electronic Systems (TODAES)
By Bernd Becker, Bettina Braitling, Ilia Polian, Juergen Schloeffel, Michel Renovell, Piet Engelke
Issue Date:August 2009
pp. 1-21
A high-performance resistive bridging fault simulator SUPERB (Simulator Utilizing Parallel Evaluation of Resistive Bridges) is proposed. It is based on fault sectioning in combination with parallel-pattern or parallel-fault multiple-stuck-at simulation. It...
     
Reducing temperature variability by routing heat pipes
Found in: Proceedings of the 19th ACM Great Lakes symposium on VLSI (GLSVLSI '09)
By Bernd Becker, Ilia Polian, Kunal P. Ganeshpure, Sandip Kundu
Issue Date:May 2009
pp. 375-376
A significant increase in power density in modern nano-electronic VLSI circuits has lead to increased localized heating and generation of hot spots. These temperature effects can lead to reliability and performance problems. This paper presents a novel des...
     
Resistive bridging fault simulation of industrial circuits
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '08)
By Bernd Becker, Ilia Polian, Juergen Schloeffel, Piet Engelke
Issue Date:March 2008
pp. 1-30
We report the successful application of a resistive bridging fault (RBF) simulator to industrial benchmark circuits. Despite the slowdown due to the consideration of the sophisticated RBF model, the run times of the simulator were within an order of magnit...
     
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