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Displaying 1-29 out of 29 total
An empirical study on efficiency and effectiveness of localized vs. Latin-based CAPTCHA challenges
Found in: Proceedings of the 17th Panhellenic Conference on Informatics (PCI '13)
By Artemios G. Voyiatzis, Christos A. Fidas
Issue Date:September 2013
pp. 91-97
A Completely Automated Public Turing test to tell Computers and Humans Apart (CAPTCHA) is a widely used security mechanism for constructing a high-confidence proof that the entity interacting with a remote service is actually a human being. We conducted an...
     
Design and Implementation of an E-exam System Based on the Android Platform
Found in: 2012 16th Panhellenic Conference on Informatics (PCI)
By George Meletiou,Ioannis Voyiatzis,Vera Stavroulaki,C. Sgouropoulou
Issue Date:October 2012
pp. 375-380
Due to the widespread adoption and use of handheld mobile devices, the application of mobile technologies in enhancing learning activities has attracted noteworthy research interest. This paper presents an attempt to exploit mobile technologies to simplify...
 
Test Set Embedding into Low-Power BIST Sequences Using Maximum Bipartite Matching
Found in: 2012 16th Panhellenic Conference on Informatics (PCI)
By I. Voyiatzis,K. Axiotis,N. Papaspyrou,H. Antonopoulou,C. Efstathiou
Issue Date:October 2012
pp. 74-79
Current trends in VLSI designs necessitate low power during both normal system operation and testing activity. Traditional Built-in Self Test (BIST) generators rise unnaturally the power consumption during testing, boosting the need to add low-power soluti...
 
Input vector monitoring on line concurrent BIST based on multilevel decoding logic
Found in: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012)
By I. Voyiatzis
Issue Date:March 2012
pp. 1251-1256
Input Vector Monitoring Concurrent Built-In Self Test (BIST) schemes provide the capability to perform testing while the Circuit Under Test (CUT) operates normally, by exploiting vectors that appear at the inputs of the CUT during its normal operation. In ...
 
A secure DTN-based smart camera surveillance system
Found in: Proceedings of the Workshop on Embedded Systems Security (WESS '11)
By Andreas Papalambrou, Artemios G. Voyiatzis, Dimitrios N. Serpanos, Panagiotis Soufrilas
Issue Date:October 2011
pp. 1-4
A smart camera surveillance system operating over a DTN network is presented. Low power embedded systems with connected smart cameras are used to detect and record events using motion and other triggers. Smart camera nodes can cooperate by means of a wirel...
     
Increasing lifetime of cryptographic keys on smartphone platforms with the controlled randomness protocol
Found in: Proceedings of the Workshop on Embedded Systems Security (WESS '11)
By Artemios G. Voyiatzis, Dimitrios N. Serpanos, Kyriakos G. Stefanidis
Issue Date:October 2011
pp. 1-6
A significant design parameter for secure embedded systems is the performance of the cryptographic algorithms implementation. We present a performance analysis on the same hardware of the cryptographic libraries available on the Google Android 2.2 and Micr...
     
An Empirical Study on the Web Password Strength in Greece
Found in: Informatics, Panhellenic Conference on
By Artemios G. Voyiatzis,Christos A. Fidas,Dimitrios N. Serpanos,Nikolaos M. Avouris
Issue Date:October 2011
pp. 212-216
Text passwords are commonly used for user authentication in the web. There is lately a strong interest for case studies on the password habits of populations with different cultures and/or languages. In this paper, we augment the existing literature with a...
 
On the necessity of user-friendly CAPTCHA
Found in: Proceedings of the 2011 annual conference on Human factors in computing systems (CHI '11)
By Artemios G. Voyiatzis, Christos A. Fidas, Nikolaos M. Avouris
Issue Date:May 2011
pp. 2623-2626
A "Completely Automated Public Turing test to tell Computers and Humans Apart" (CAPTCHA) is a mechanism widely used nowadays for protection of web applications, interfaces, and services from malicious users. A questionnaire-based survey combined with a rea...
     
A Novel SRAM-Cell Based Input Vector Monitoring Concurrent BIST Architecture
Found in: European Test Symposium, IEEE
By I. Voyiatzis, C. Efstathiou, H. Antonopoulou
Issue Date:May 2011
pp. 206
Input vector monitoring concurrent Built-In Self-Test (BIST) schemes can circumvent problems appearing separately in on-line and off-line BIST techniques. The concurrent test latency of an input vector monitoring concurrent BIST scheme is the time required...
 
When Security Meets Usability: A User-Centric Approach on a Crossroads Priority Problem
Found in: Informatics, Panhellenic Conference on
By Christos A. Fidas, Artemios G. Voyiatzis, Nikolaos M. Avouris
Issue Date:September 2010
pp. 112-117
Effective and efficient methodologies are essential for developing and maintaining information systems that are both secure and usable, especially in the case of Internet applications that require a combined effort from application, system, network, securi...
 
On Embedding Test Sets into Hardware Generated Sequences
Found in: Informatics, Panhellenic Conference on
By D. Kavvadias, S. Sinitos, I. Voyiatzis, H. Antonopoulou, C. Efstathiou
Issue Date:September 2010
pp. 158-163
In this paper a novel algorithm is presented for embedding test sets containing don’t care values into sequences generated by binary counters. Experiments carried out on randomly generated test sets reveal that the proposed scheme results in shorter test s...
 
Embedding Test Patterns in Accumulator-Generated Sequences in O(1) Time
Found in: Informatics, Panhellenic Conference on
By Nestor Ioannidis, Ioannis Voyiatzis
Issue Date:September 2009
pp. 55-59
In test set embedding Built-In Self Test schemes the test set is embedded into the sequence generated by the BIST pattern generator. Single-seed embedding schemes embed the test set into a single sequence. This calls for a need to evaluate the location of ...
 
An Input Vector Monitoring Concurrent BIST scheme exploiting
Found in: On-Line Testing Symposium, IEEE International
By I. Voyiatzis, D. Gizopoulos, A. Paschalis
Issue Date:June 2009
pp. 206-207
Input Vector Monitoring Concurrent Built-In Self Test schemes provide the capability to perform testing while the Circuit Under Test operates normally, by exploiting vectors that appear at the inputs of the CUT during its normal operation. The Concurrent T...
 
A Low-Cost Accumulator-Based Test Pattern Generation Architecture
Found in: On-Line Testing Symposium, IEEE International
By Dimitrios Magos, Ioannis Voyiatzis, Steffen Tarnick
Issue Date:July 2008
pp. 267-272
A novel scheme for reducing the test application time in accumulator-based test-pattern generation is presented. The proposed scheme exhibits extremely low demand for hardware. It is based on a decoder whose inputs are driven by a very slow external tester...
 
The security of the Fiat--Shamir scheme in the presence of transient hardware faults
Found in: ACM Transactions on Embedded Computing Systems (TECS)
By Artemios G. Voyiatzis, Dimitrios N. Serpanos
Issue Date:April 2008
pp. 1-13
Implementation cryptanalysis has emerged as a realistic threat for cryptographic systems. It consists of two classes of attacks: fault-injection and side-channel attacks. In this work, we examine the resistance of the Fiat--Shamir scheme to fault-injection...
     
An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set
Found in: IEEE Transactions on Computers
By Ioannis Voyiatzis, Antonis Paschalis, Dimitris Gizopoulos, Constantin Halatsis, Frosso S. Makri, Miltiadis Hatzimihail
Issue Date:August 2008
pp. 1012-1022
Built-In Self-Test (BIST) techniques constitute an effective and practical approach for VLSI circuits testing. BIST schemes are typically classified into two categories: off-line and on-line. Input vector monitoring concurrent BIST schemes are a class of o...
 
An ALU-Based BIST Scheme for Word-Organized RAMs
Found in: IEEE Transactions on Computers
By Ioannis Voyiatzis
Issue Date:May 2008
pp. 577-590
Word-organized memories are typically tested by repeatedly applying a test for bit-oriented memories using different data backgrounds (which depend on the used intra-word fault model), resulting in limited fault coverage. In this paper a new approach for t...
 
Embedding test patterns into Low-Power BIST sequences
Found in: On-Line Testing Symposium, IEEE International
By Ioannis Voyiatzis
Issue Date:July 2007
pp. 197-198
Current trends in VLSI designs necessitate low power during both normal system operation and testing activity. Traditional Built-in Self Test (BIST) generators rise the power and energy consumption during testing, boosting the need to add low-power solutio...
   
A concurrent BIST scheme for on-line/off-line testing based on a pre-computed test set
Found in: Test Conference, International
By I. Voyiatzis, D. Gizopoulos, A. Paschalis, C. Halatsis
Issue Date:November 2005
pp. 8 pp.-1125
Manufacturing testing is carried-out once in order to ensure the correct operation of the circuit under test right after fabrication, while either periodic off-line testing or concurrent on-line testing is carried-out in order to ensure that the circuit un...
 
Accumulator-Based Weighted Pattern Generation
Found in: On-Line Testing Symposium, IEEE International
By I. Voyiatzis, D. Gizopoulos, A. Paschalis
Issue Date:July 2005
pp. 215-220
<p>Weighted pseudorandom BIST schemes have been efficiently utilized in order to drive down the number of vectors required to achieve complete fault coverage in Built in Self Test (BIST) applications. Sets of patterns comprising weights 0, 0.5 and 1 ...
 
A Low-Cost Concurrent BIST Scheme for Increased Dependability
Found in: IEEE Transactions on Dependable and Secure Computing
By Ioannis Voyiatzis, Constantin Halatsis
Issue Date:April 2005
pp. 150-156
Built-In Self-Test (BIST) techniques constitute an attractive and practical solution to the difficult problem of testing VLSI circuits and systems. Input vector monitoring concurrent BIST schemes can circumvent problems appearing separately in online and i...
 
Test Vector Embedding into Accumulator-Generated Sequences: A Linear-Time Solution
Found in: IEEE Transactions on Computers
By Ioannis Voyiatzis
Issue Date:April 2005
pp. 476-484
The test set embedding problem is typically formed as follows: Given an n-stage pattern generator and a test set, calculate the minimum number of steps that the generator needs to operate in order to generate all vectors in the test set. The cornerstone of...
 
A Fault-Injection Attack on Fiat-Shamir Cryptosystems
Found in: Distributed Computing Systems Workshops, International Conference on
By Artemios G. Voyiatzis, Dimitrios N. Serpanos
Issue Date:March 2004
pp. 618-621
<p>Fault-injection attacks and cryptanalysis is a realistic threat for systems implementing cryptographic algorithms. We revisit the fault-injection attacks on the Fiat-Shamir authentication scheme, a popular authentication scheme for service provide...
 
Pulse: A Class of Super-Worms against Network Infrastructure
Found in: Distributed Computing Systems Workshops, International Conference on
By A.G. Voyiatzis, D.N. Serpanos
Issue Date:May 2003
pp. 28
<p>Super-worms constitute the most advanced and dangerous threat for networks and the whole Internet. Their goal is to infect the significant majority of Internet hosts in the minimum possible time, by using advanced techniques to partition the Inter...
 
Secure network design: A layered approach
Found in: Autonomous Decentralized System, International Workshop on
By D.N. Serpanos, A.G. Voyiatzis
Issue Date:November 2002
pp. 95-100
Security solutions for networks typically appear as single protocols, or protocols that correspond to a single layer of the OSI network reference model (protocol stack). The result is a wide variety of protocols which provide solutions to very specific pro...
 
Active Hardware Attacks and Proactive Countermeasures
Found in: Computers and Communications, IEEE Symposium on
By Artemios G. Voyiatzis, Dimitrios N. Serpanos
Issue Date:July 2002
pp. 361
<p>Active hardware attacks succeed in deriving cryptographic secrets from target devices. They were originally proposed for systems implementing RSA, Fiat-Shamir scheme, and Schnorr?s scheme.Common targets for these attacks are systems used for clien...
 
R-CBIST: An Effective RAM-based Input Vector Monitoring Concurrent BIST Technique
Found in: Test Conference, International
By I. Voyiatzis, A. Paschalis, D. Nikolos, C. Halatsis
Issue Date:October 1998
pp. 918
In this paper a novel Input Vector Monitoring Concurrent BIST technique based on a RAM (R-CBIST) is presented. This technique compares favorably to the other input vector monitoring concurrent BIST techniques proposed so far with respect to the hardware ov...
 
An efficient comparative concurrent Built-In Self-Test technique
Found in: Asian Test Symposium
By I. Voyiatzis, D. Nikolos, A. Paschalis, C. Halatsis, T. Haniotakis
Issue Date:November 1995
pp. 309
Built-In Self-Test (BIST) techniques constitute an attractive and practical solution to the difficult problem of testing VLSI circuits and systems. Among the BIST techniques the Comparative Concurrent BIST (C-BIST) has various advantages since it provides ...
 
Accumulator-based BIST approach for stuck-open and delay fault testing
Found in: European Design and Test Conference
By I. Voyiatzis, A. Paschalis, D. Nikolos, C. Halatsis
Issue Date:March 1995
pp. 431
In this paper a novel accumulator-based Built-In Self Test (BIST) method for complete two-pattern test generation is presented. Complete two-pattern testing has been proposed for stuck-open and delay testing. The proposed scheme is very attractive for a wi...
 
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