Search For:

Displaying 1-50 out of 215 total
Dynamic fault test and diagnosis in digital systems using multiple clock schemes and multi-VDD test
Found in: 11th IEEE International On-Line Testing Symposium
By M. Rodriguez-Irago,J.J. Rodriguez Andina,F. Vargas,M.B. Santos,I.C. Teixeira,J.P. Teixeira
Issue Date:May 2014
pp. 281,282,283,284,285,286
Performance test is a powerful technique to identify difficult to detect defects. Recently, the authors have shown that multi-V/sub DD/ test schemes may be used in a BIST environment to simulate multi-clock test. Using circuit and logic-level fault simulat...
 
The influence of clock-gating on NBTI-induced delay degradation
Found in: 2012 IEEE 18th International On-Line Testing Symposium (IOLTS 2012)
By J. Pachito,C. V. Martins,J. Semiao,M. Santos,I. C. Teixeira,J. P. Teixeira
Issue Date:June 2012
pp. 61-66
This paper presents an analysis of the implications of clock gating techniques on the increase of aging degradations in new node digital circuits. NBTI is the dominant effect that cause long-term performance degradations over time, and circuit operating co...
 
Protein Classification with Extended-Sequence Coding by Sliding Window
Found in: IEEE/ACM Transactions on Computational Biology and Bioinformatics (TCBB)
By Antonio Padua Braga, Fernanda Caldas Cardoso, Fernanda Caldas Cardoso, Santuza Maria Ribeiro Teixeira, Santuza Maria Ribeiro Teixeira, Sergio Costa Oliveira, Sergio Costa Oliveira, Thiago de Souza Rodrigues, Thiago de Souza Rodrigues
Issue Date:November 2011
pp. 1721-1726
A large number of unclassified sequences is still found in public databases, which suggests that there is still need for new investigations in the area. In this contribution, we present a methodology based on Artificial Neural Networks for protein function...
     
Performance Failure Prediction Using Built-In Delay Sensors in FPGAs
Found in: International Conference on Field Programmable Logic and Applications
By V. Bexiga,C. Leong,J. Semião,I.C. Teixeira,J.P. Teixeira,M. Valdés,J. Freijedo,J.J. Rodríguez-Andina,F. Vargas
Issue Date:September 2011
pp. 301-304
The objective of this paper is to propose a performance failure prediction methodology for FPGA-based designs, based on the use of a novel built-in programmable delay sensor. Digital Clock Managers (DCM) is used to fine tune the unsafe observation interval...
 
Modeling the effect of process variations on the timing response of nanometer digital circuits
Found in: Latin American Test Workshop
By J. Freijedo,J. Semiao,J. J. Rodriguez-Andina,F. Vargas,I. C. Teixeira,J. P. Teixeira
Issue Date:March 2011
pp. 1-5
The implementation of complex, high-performance functionality in nano-CMOS technologies faces significant design and test challenges related to the increased susceptibility to process variations and environmental or operation-dependent disturbances. This p...
 
On-line BIST for performance failure prediction under aging effects in automotive safety-critical applications
Found in: Latin American Test Workshop
By R. S. Oliveira,J. Semiao,I. C. Teixeira,M. B. Santos,J. P. Teixeira
Issue Date:March 2011
pp. 1-6
Electronic design of high-performance digital systems in nano-scale CMOS technologies under Process, power supply Voltage, Temperature and Aging (PVTA) variations is a challenging process. Such variations induce abnormal timing delays leading to systems er...
 
Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects
Found in: Latin American Test Workshop
By M. Valdes,J. Freijedo,M. J. Moure,J. J. Rodriguez-Andina,J. Semiao,F. Vargas,I. C. Teixeira,J. P. Teixeira
Issue Date:March 2011
pp. 1-7
In current nanometer technologies, aging effects (due for instance to Negative Bias Thermal Instability) may appear after relatively short operating times, compared to the expected lifetime of circuits, even for relatively short-cycle consumer electronics....
 
Predictive error detection by on-line aging monitoring
Found in: On-Line Testing Symposium, IEEE International
By J. C. Vazquez, V. Champac, A. M. Ziesemer, R. Reis, J. Semiao, I. C. Teixeira, M. B. Santos, J. P. Teixeira
Issue Date:July 2010
pp. 9-14
The purpose of this paper is to present a predictive error detection methodology, based on monitoring of long-term performance degradation of semiconductor systems. Delay variation is used to sense timing degradation due to aging (namely, due to NBTI), or ...
 
Investigating the Use of BICS to detect resistive-open defects in SRAMs
Found in: On-Line Testing Symposium, IEEE International
By R. Chipana, L. Bolzani, F. Vargas, J. Semiao, J. Rodriguez-Andina, I. Teixeira, P. Teixeira
Issue Date:July 2010
pp. 200-201
Technology scaling has changed the Static Random Access Memory (SRAM) test scenario, leading to an insufficiency of the usually adopted functional fault models. In this sense, these fault models are no longer able to correctly reproduce the effects caused ...
 
Built-in Clock Domain Crossing (CDC) test and diagnosis in GALS systems
Found in: Design and Diagnostics of Electronic Circuits and Systems
By C. Leong, P. Machado, V. Bexiga, J. P. Teixeira, I. C. Teixeira, J. C. Silva, P. Lousa, J. Varela
Issue Date:April 2010
pp. 72-77
The purpose of this paper is to present a novel built-in Clock Domain Crossing (CDC) test and diagnosis methodology for Globally Asynchronous, Locally Synchronous (GALS) systems. The methodology allows design and prototype validation, low maintenance and r...
 
Identification of Regulatory Modules in Time Series Gene Expression Data Using a Linear Time Biclustering Algorithm
Found in: IEEE/ACM Transactions on Computational Biology and Bioinformatics (TCBB)
By Arlindo L. Oliveira, Isabel Sa-Correia, Isabel Sa-Correia, Miguel C. Teixeira, Miguel C. Teixeira, Sara C. Madeira, Sara C. Madeira
Issue Date:January 2010
pp. 153-165
Although most biclustering formulations are NP-hard, in time series expression data analysis, it is reasonable to restrict the problem to the identification of maximal biclusters with contiguous columns, which correspond to coherent expression patterns sha...
     
Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies
Found in: On-Line Testing Symposium, IEEE International
By J. Semiao, J. Freijedo, J. Rodriguez-Andina, F. Vargas, M. Santos, I. Teixeira, P. Teixeira
Issue Date:June 2009
pp. 223-228
In nanometer technologies, as variability is becoming one of the leading causes for chip failures, signal integrity is a key issue for high-performance digital System-on-Chip (SoC) products. In this paper, analysis is focused on the occurrence of Delay-fau...
 
Built-in aging monitoring for safety-critical applications
Found in: On-Line Testing Symposium, IEEE International
By J.C. Vazquez, V. Champac, A.M. Ziesemer, R. Reis, I.C. Teixeira, M.B. Santos, J.P. Teixeira
Issue Date:June 2009
pp. 9-14
Complex electronic systems for safety or mission-critical applications (automotive, space) must operate for many years in harsh environments. Reliability issues are worsening with device scaling down, while performance and quality requirements are increasi...
 
Signal Integrity Enhancement in Digital Circuits
Found in: IEEE Design & Test of Computers
By Jorge Filipe L C Semia̅o,Leonardo Bisch Piccoli,Fabian Luis Vargas,Marcial Jesus Rodriguez Irago,Juan J Rodriguez-Andina,Marcelino Bicho dos Santos,Isabel Maria Cacho Teixeira,Joao Paulo Teixeira
Issue Date:September 2008
pp. 452-461
This article proposes a new methodology for enhancing SoC signal integrity without degrading performance in the presence of power-ground voltage transients. The underlying principle is the dynamic adaptation of the clock duty cycle to propagation delay var...
 
Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits
Found in: On-Line Testing Symposium, IEEE International
By Jorge Semião, Judit Freijedo, Juan Jose Rodríguez-Andina, Fabian Vargas, Marcelino Santos, Isabel Teixeira, João Paulo Teixeira
Issue Date:July 2008
pp. 227-232
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodolog...
 
Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits
Found in: Design and Diagnostics of Electronic Circuits and Systems
By J. Semiao, J. J. Rodriguez-Andina, F. Vargas, M. Santos, I. Teixeira, P. Teixeira
Issue Date:April 2008
pp. 1-4
This paper describes a thermal and power-supply tolerant design methodology for pipeline based circuits. It is shown that by making the circuit more tolerant to V<inf>DD</inf> and temperature (T) instability, even in the presence of process var...
 
Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By J. Semião, J. J. Rodríguez-Andina, F. Vargas, M. B. Santos, I. C. Teixeira, J. P. Teixeira
Issue Date:September 2007
pp. 303-311
A new methodology is proposed to increase the robustness of pipeline-based circuits. The goal is to improve signal integrity in the presence of power-supply voltage (VDD) and/or temperature (T) variations, without degrading circuit performance. In the prop...
 
On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits
Found in: On-Line Testing Symposium, IEEE International
By J. Semião, J. Freijedo, J.J. Rodríguez-Andina, F. Vargas, M.B. Santos, I.C. Teixeira, J.P. Teixeira
Issue Date:July 2007
pp. 167-172
In this paper, a new methodology is proposed to improve digital circuit signal integrity, in the presence of power-supply voltage (VDD) and temperature (T) variations. The underlying principle of the proposed methodology is to introduce on-line additional ...
 
Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits
Found in: Design and Diagnostics of Electronic Circuits and Systems
By J. Semiao, J. Freijedo, J. J. Rodriguez-Andina, F. Vargas, M. B. Santos, I. C. Teixeira, J. P. Teixeira
Issue Date:April 2007
pp. 1-6
As IC technology scales down, power supply voltage and temperature variations play an increasing role in signal integrity loss, which lead to performance degradation, reliability problems and functional errors. In this paper, we propose a new methodology t...
 
Enhancing the Tolerance to Power-Supply Instability in Digital Circuits
Found in: VLSI, IEEE Computer Society Annual Symposium on
By J. Semiao, J. Freijedo, J.J. Rodríguez Andina, F. Vargas, M. B. Santos, I. C. Teixeira, J. P. Teixeira
Issue Date:March 2007
pp. 207-212
As IC technology scales down, power supply instability may dramatically contribute to signal integrity loss. In this paper, we propose a new methodology to enhance circuit tolerance to powersupply voltage (VDD) local variations, without degrading its perfo...
 
Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes
Found in: On-Line Testing Symposium, IEEE International
By M. Rodríguez-Irago, J.J. Rodríguez Andina, F. Vargas, J. Semião, I.C. Teixeira, J.P. Teixeira
Issue Date:July 2006
pp. 257-262
Detection of physical defects (or transient faults) in nanometer products is very challenging. Parametric test, using variable power supply voltage, clock frequency and temperature can be rewarding. However, their impact on digital system performance needs...
 
Design and test methodology for a reconfigurable PEM data acquisition electronics system
Found in: International Conference on Field Programmable Logic and Applications
By C. Leong, P. Bento, J.P. Teixeira, I.C. Teixeira, P. Rodrigues, A. Trindade, J.C. Silva, J. Varela, J. Rego, J. Nobre, P. Lousa
Issue Date:August 2005
pp. 523-526
The purpose of this paper is to present the main aspects of a design and test (D&T) methodology used in the development of a specific type of system. The application focuses medical imaging using a compact positron emission mammography (PEM) detector w...
 
Design and test issues of a FPGA based data acquisition system for medical imaging using PEM
Found in: IEEE-NPSS Real Time Conference
By C. Leong, P. Bento, P. Rodrigues, J.C. Silva, A. Trindade, P. Lousa, J. Rego, J. Nobre, J. Varela, J.P. Teixeira, C. Teixeira
Issue Date:June 2005
pp. 92
The main aspects of the design and test (D&T) of a reconfigurable architecture for the data acquisition electronics (DAE) system of the clear-PEM detector are presented in this paper. The application focuses medical imaging using a compact PEM (positro...
 
Modeling and Simulation of Time Domain Faults in Digital Systems
Found in: On-Line Testing Symposium, IEEE International
By D. Barros Júnior, F. Vargas, M. B. Santos, I. C. Teixeira, J. P. Teixeira
Issue Date:July 2004
pp. 5
The purpose of this paper is to present and discuss a novel modeling and fault simulation technique for two types of dynamic faults in digital systems: transient power supply voltage drops and transient delays in logic elements or signals paths. Techniques...
 
RTL Test Pattern Generation for High Quality Loosely Deterministic BIST
Found in: Design, Automation and Test in Europe Conference and Exhibition
By M. B. Santos, J. M. Fernandes, I. C. Teixeira, J. P. Teixeira
Issue Date:March 2003
pp. 10994
High quality Built-In Self Test (BIST) needs to efficiently tackle the coverage of random-pattern-resistant (r.p.r) defects. Several techniques have been proposed to cover r.p.r faults at logic level, namely, weighted pseudo-random and mixed-mode. In mixed...
 
Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By F.M. Gonçalves, M. B. Santos, I. C. Teixeira, J. P. Teixeira
Issue Date:November 2002
pp. 216
The computational effort associated with Fault Simulation (FS) processes in digital systems can become overwhelming, due to circuit complexity, test pattern size or fault list size. The same applies when safety properties (such as fault tolerance or fail-s...
 
RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST
Found in: Test Conference, International
By M.B. Santos, I.C. Teixeira, J.P. Teixeira, S. Manich, R. Rodriquez, J. Figueras
Issue Date:October 2002
pp. 814
While high-quality BIST (Built-In Self Test) based on deterministic vectors often has a prohibitive cost, pseudo-random based BIST may lead to low DC (Defects Coverage) values, requiring however very long test sequences with the corresponding energy waste ...
 
Implicit Functionality and Multiple Branch Coverage (IFMB): a Testability Metric for RT-Level
Found in: Test Conference, International
By M. B. Santos, F.M. Gonçalves, I.C. Teixeira, J. P. Teixeira
Issue Date:November 2001
pp. 377
The purpose of this paper is to introduce a new RTL testability metric, IFMB, that evaluates the exercise of Implicit Functionality (IF) of operators and Multiple Branch (MB) coverage of conditional constructs. Although physical Defect Coverage (DC) strong...
 
Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Control
Found in: On-Line Testing Workshop, IEEE International
By F.M. Gonçalves, M.B. Santos, I.C. Teixeira, J. P. Teixeira
Issue Date:July 2001
pp. 0197
Abstract: The purpose of this paper is to present a methodology and tools for the design and test of a EN298 compliant ASIC chip for safety-critical gas burner control. Safe operation, as far as the critical variable is concerned, is guaranteed in the pres...
 
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage
Found in: European Test Workshop, IEEE
By M.B. Santos, F.M. Gonçalves, I.C. Teixeira, J.P. Teixeira
Issue Date:June 2001
pp. 99
The purpose of this paper is to present a RTL design and test methodology allowing the identification of design errors and difficult to verify functional parts.Using novel RTL fault models (namely, for arithmetic and relational operators) and Testability M...
 
Test Resource Partitioning: A Design and Test Issue
Found in: Design, Automation and Test in Europe Conference and Exhibition
By J.P. Teixeira, I.M. Teixeira, O.P. Dias, J. Semião, C.E. Pereira
Issue Date:March 2001
pp. 0034
Abstract: Product development economics and specs drive the need for on chip embedded test functionality. However, optimal partitioning of test functionality between a tester and a SOC is a non-trivial task, which must be solved during the system analysis ...
   
RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs
Found in: European Test Workshop, IEEE
By M. B. Santos, F.M. Gonçalves, I.C. Teixeira, J. P. Teixeira
Issue Date:May 2000
pp. 99
Functional test is long viewed as unfitted for production test. The purpose of this contribution is to propose an RTL-based test generation methodology, which can be rewardingly, used both for design validation and to enhance the test effectiveness of clas...
 
Quality of Electronic Design: From Architectural Level to Test Coverage
Found in: Quality Electronic Design, International Symposium on
By O.P. Dias, J. Semião, M.B. Santos, I.M. Teixeira, J.P. Teixeira
Issue Date:March 2000
pp. 197
The purpose of this paper is to present a design methodology that complements existing methodologies by addressing the upper and the lower extremes of the design flow. The aim of the methodology is to increase design and product quality. At system level, e...
 
MOSYS A Methodology for Automatic Object Identification from System Specification
Found in: Object-Oriented Real-Time Distributed Computing, IEEE International Symposium on
By L.B. Becker, C.E. Pereira, O.P. Dias, I.M. Teixeira, J.P. Teixeira
Issue Date:March 2000
pp. 198
This paper presents a new approach to the automatic identification of objects/classes from a system specification. The methodology is aimed at the development of Distributed Real-Time Systems (DRTS), specially those conceived for industrial automation appl...
 
Hardware/Software Specification, Design and Test using a System Level Approach
Found in: Integrated Circuit Design and System Design, Symposium on
By O.P. Dias, J. Semião, C.E. Pereira, I.M. Teixeira, J.P. Teixeira
Issue Date:October 1999
pp. 0042
The purpose of this paper is to present an environment that allows the reliable, in-time system specification and design of complex hardware/software (hw/sw) systems. The Object Oriented (OO) paradigm underlies models, methodologies, languages and tools. T...
 
From System Level to Defect-Oriented Test: A Case Study
Found in: European Test Workshop, IEEE
By J. Semião, M.B. Santos, I.M. Teixeira, J.P. Teixeira
Issue Date:September 1999
pp. 136
The purpose of this paper is to demonstrate the usefulness of a recently proposed Object-Oriented (OO) based methodology and tools (SysObj and Test-Adder) when applied in the design of testable hardware modules (eventually used as embedded cores in SOCs). ...
 
Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique
Found in: VLSI Test Symposium, IEEE
By M.B. Santos, F.M. Gongalves, I.C. Teixeira, J.P. Teixeira
Issue Date:April 1999
pp. 326
No summary available.
 
Defect-Oriented Test Quality Assessment using Fault Sampling and Simulation
Found in: Test Conference, International
By F.M. Gonçalves, M.B. Santos, I.C. Teixeira, J. P. Teixeira
Issue Date:October 1998
pp. 35
The purpose of this paper is to present a novel methodology for the estimation of VLSI products Defect Level, or reject rates, in the IC design environment. A new Defect-Oriented (DO) fault extraction and stratified sampling technique, implemented in an ex...
 
Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By F.M. Goncalves, I.C. Teixeira, J.P. Teixeira
Issue Date:October 1997
pp. 29
The purpose of this paper is to present a methodology for circuit and realistic fault extraction, and its implementation in a new tool, lobs, to be included in a virtual test environment, DOTLab. Digital, analog and mixed signal ICs, implemented in CMOS, b...
 
Joint control of MPEG VBR video over ATM networks
Found in: Image Processing, International Conference on
By L. Teixeira, T. Andrade, V. Teixeira
Issue Date:October 1997
pp. 586
In video applications, digital encoding techniques are frequently associated to the use of compression algorithms. Compression algorithms such as the MPEG 2 standard allow economies in transmission bandwidth, while providing a service with a quality simila...
 
Integrated Approach for Circuit and Fault Extraction of VLSI Circuits
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By F.M. Goncalves, I.C. Teixeira, J.P. Teixeira
Issue Date:November 1996
pp. 96
No summary available.
 
HW/SW specification using OOM techniques
Found in: Rapid System Prototyping, IEEE International Workshop on
By M. Calha, J.P. Teixeira, I.C. Teixeira
Issue Date:June 1996
pp. 96
The ever increasing complexity and networking of hardware/software (hw/sw) systems, together with tough competitiveness and shrinking time-to-market puts a heavy burden on system design methodologies. For rapid system prototyping, design productivity is ma...
 
Test preparation for high coverage of physical defects in CMOS digital ICs
Found in: VLSI Test Symposium, IEEE
By M.B. Santos, M. Simoes, I. Teixeira, J.P. Teixeira
Issue Date:May 1995
pp. 0330
Abstract: In this paper, a novel methodology for test preparation of digital ICs, aiming at high defect coverage and affordable computational effort, is proposed. A method is presented to heuristically generate a list of pseudo realistic (PSE) faults, at g...
 
Test preparation methodology for high coverage of physical defects in CMOS digital ICs
Found in: European Design and Test Conference
By M.B. Santos, M. Simoes, I. Teixeira, J.P. Teixeira
Issue Date:March 1995
pp. 604
The constant increase of IC circuit complexity and quality requirements make high quality testing a difficult challenge. In this work, a methodology for test preparation leading to high physical defect coverage is proposed. Two new software tools are prese...
   
Datacenter in a Box: Test Your SDN Cloud-Datacenter Controller at Home
Found in: 2013 Second European Workshop on Software Defined Networks (EWSDN)
By Jose Teixeira,Gianni Antichi,Davide Adami,Alessio Del Chiaro,Stefano Giordano,Alexandre Santos
Issue Date:October 2013
pp. 99-104
In the last years, the widespread of Cloud computing as the main paradigm to deliver a large plethora of virtualized services significantly increased the complexity of Datacenters management and raised new performance issues for the intra-Datacenter networ...
 
Coevolution of variability models and related artifacts: a case study from the Linux kernel
Found in: Proceedings of the 17th International Software Product Line Conference (SPLC '13)
By Andrzej Wąsowski, Jianmei Guo, Krzysztof Czarnecki, Leonardo Passos, Leopoldo Teixeira, Paulo Borba
Issue Date:August 2013
pp. 91-100
Variability-aware systems are subject to the coevolution of variability models and related artifacts. Surprisingly, little knowledge exists to understand such coevolution in practice. This shortage is directly reflected in existing approaches and tools for...
     
Probabilistic Testability Analysis and DFT Methods at RTL
Found in: 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
By J.M. Fernandes,M.B. Santos,A.L. Oliveira,J.C. Teixeira
Issue Date:August 2013
pp. 214-215
This work presents probabilistic methods for testability analysis at RTL and their use to guide DFT techniques like partial-scan and TPI. Controllability is analyzed using an approach that takes into account correlations within pre-defined groups formed ba...
 
Web performance bottlenecks in broadband access networks
Found in: Proceedings of the ACM SIGMETRICS/international conference on Measurement and modeling of computer systems (SIGMETRICS '13)
By Nazanin Magharei, Nick Feamster, Renata Teixeira, Sam Crawford, Srikanth Sundaresan
Issue Date:June 2013
pp. 383-384
We present the first large-scale analysis of Web performance bottlenecks as measured from broadband access networks, using data collected from extensive home router deployments. We analyze the limits of throughput on improving Web performance and identify ...
     
A statistical decision tree algorithm for medical data stream mining
Found in: 2013 IEEE 26th International Symposium on Computer-Based Medical Systems (CBMS)
By Mirela Teixeira Cazzolato,Marcela Xavier Ribeiro
Issue Date:June 2013
pp. 389-392
The use of computational resources can improve the diagnosis of medical diseases as a second opinion. Due to the large amount of data obtained daily, incremental techniques have been proposed to process medical data stream. In this paper we present an incr...
   
Predicting visualization of hospital clinical reports using survival analysis of access logs from a virtual patient record
Found in: 2013 IEEE 26th International Symposium on Computer-Based Medical Systems (CBMS)
By Pedro Pereira Rodrigues,Claudia Camila Dias,Diana Rocha,Isabel Boldt,Armando Teixeira-Pinto,Ricardo Cruz-Correia
Issue Date:June 2013
pp. 461-464
The amount of data currently being produced, stored and used in hospital settings is stressing information technology infrastructure, making clinical reports to be stored in secondary memory devices. The aim of this work was to develop a model that predict...
   
 1  2 Next >>