Search For:

Displaying 1-9 out of 9 total
A Power Efficient and Compact Optical Interconnect for Network-on-Chip
Found in: IEEE Computer Architecture Letters
By Zheng Chen,Huaxi Gu,Yintang Yang,Luying Bai,Hui Li
Issue Date:January 2014
pp. 1-1
Optical interconnect is a promising alternative to substitute the electrical interconnect for intra-chip communications. The topology of optical Network-on-Chip (ONoC) has a great impact on the network performance. However, the size of ONoC is limited by t...
A New Approach to Multi-objective Virtual Machine Placement in Virtualized Data Center
Found in: 2013 IEEE 8th International Conference on Networking, Architecture, and Storage (NAS)
By Sinong Wang,Huaxi Gu,Gang Wu
Issue Date:July 2013
pp. 331-335
In this paper, a virtual machine placement model to maximize resource utilization, balance multi-dimensional re-sources use and minimize communication traffic simultaneously within the data center is proposed. The multi-objective problem is simplified by e...
A partially adaptive routing algorithm for Benes network on chip
Found in: Computer Science and Information Technology, International Conference on
By Jing Zhang,Huaxi Gu
Issue Date:August 2009
pp. 614-618
The Benes topology is one of the choices for network on chip system designer for its simple topology and easy scalability with low degree. Routing algorithm plays an important role in the network performance of Benes network. However, traditional routing a...
A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Huaxi Gu, Kwai Hung Mo, Jiang Xu, Wei Zhang
Issue Date:May 2009
pp. 19-24
Networks-on-chip (NoCs) can improve the communication bandwidth and power efficiency of multiprocessor systems-on-chip (MPSoC). However, traditional metallic interconnects consume significant amount of power to deliver even higher communication bandwidth r...
Performance Modeling of Fully Adaptive Wormhole Routing in 2D-Mesh Network-on-Chip with MMPP (2) Input Traffic
Found in: Information Science and Engieering, International Symposium on
By Yonghui Li, Huaxi Gu, Peibo Xie, Keqiang He
Issue Date:December 2008
pp. 58-62
Analytical models for fully adaptive wormhole routing in k-ary n-cubes interconnection networks have been widely reported in the literature. However, there are few performance models for 2D-mesh Network-on-Chip. Most current models assume Poisson traffic, ...
A New Inner Congestion Control Mechanism in Terabit Routers
Found in: Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing, ACIS International Conference on
By Huaxi Gu, Kun Wang, Chu Ke, Changshan Wang, Guochang Kang
Issue Date:August 2007
pp. 178-181
Direct interconnection network (DIN) has gained more and more attention when designing the switching fabric in the terabit routers. Various congestion control mechanisms are proposed for DIN when it is employed in the parallel computer systems. However, th...
A New Routing Method to Tolerate both Convex and Concave
Found in: Parallel and Distributed Computing Applications and Technologies, International Conference on
By Huaxi Gu, Zengji Liu, Guochang Kang, Hong Shen
Issue Date:December 2005
pp. 714-719
To make the exiting fault routing algorithms tolerate concave fault regions without disabling any healthy nodes, the concept of hole is proposed in this paper. A hole consists of healthy nodes in the concave parts and neighborhood of a given concave fault ...
Analyzing Packet-Level Routing in Data Centers
Found in: 2013 IEEE International Conference on Dependable, Autonomic and Secure Computing (DASC)
By Ruoyan Liu,Huaxi Gu,Yawen Chen,Haibo Zhang
Issue Date:December 2013
pp. 648-652
Data centers host diverse applications with stringent QoS requirements. The key issue is to eliminate network congestions which severely degrade application performance. One effective solution is to balance the traffic load in the datacenter regular topolo...
ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip
Found in: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis (CODES/ISSS '08)
By Huaxi Gu, Jiang Xu, Zheng Wang
Issue Date:October 2008
pp. 1001-1001
The performance of system-on-chip is determined not only by the performance of its functional units, but also by how efficiently they cooperate with one another. It is the on-chip communication architecture which determines the cooperation efficiency. Netw...