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Displaying 1-14 out of 14 total
Performance Evaluation of Asynchronous Circuits with Choice Using Abstract Probabilistic Timed Petri Nets
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Mehrdad Najibi, Mahtab Niknahad, Hossein Pedram
Issue Date:March 2007
pp. 422-427
A framework for evaluating the performance of asynchronous systems is presented. Due to the dependencies among highly concurrent events performance evaluation of asynchronous circuits is a challenging process. The presented performance model is a Probabili...
 
HCMTT: Hybrid clustering for multi-target tracking in Wireless Sensor Networks
Found in: Pervasive Computing and Communications Workshops, IEEE International Conference on
By Faezeh Hajiaghajani,Marjan Naderan,Hossein Pedram,Mehdi Dehghan
Issue Date:March 2012
pp. 889-894
Mobile Target Tracking is viewed as one of the primary applications in Wireless Sensor Networks (WSNs). Due to WSNs' special characteristics, there happens to be a trade-off between tracking accuracy and energy consumption. We propose an efficient multi-ta...
 
A Novel Multi Channel Sensor Network MAC Protocol
Found in: Systems and Networks Communication, International Conference on
By Ali Chodari Khosrowshahi, Mehdi Dehghan, Hossein Pedram, Mohammad Alizadeh
Issue Date:September 2009
pp. 230-235
This paper proposes a media access control (MAC)layer protocol scheme that is suitable for characteristics of sensornetworks (SNs). Among important attributes of SNs arelimitation on power consumption, high density of nodes andtopology changes. Based on ti...
 
Statistical static performance analysis of asynchronous circuits considering process variation
Found in: Quality Electronic Design, International Symposium on
By Mohsen Raji, Behnam Ghavami, Hossein Pedram
Issue Date:March 2009
pp. 291-296
Asynchronous logic is a hot topic due to its interesting features of power saving, low noise and robustness to parameters variations. Beside of the benefits of asynchronous design technique, the lack of automatic design and analysis tools made it hard to a...
 
Design of dual threshold voltages asynchronous circuits
Found in: Low Power Electronics and Design, International Symposium on
By Behnam Ghavami, Hossein Pedram
Issue Date:August 2008
pp. 185-188
This paper introduces a framework for the minimization of leakage power consumption of asynchronous circuits via using dual threshold voltages technique. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the c...
 
A Power Estimation Methodology for QDI Asynchronous Circuits based on High-Level Simulation
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Mahtab Niknahad, Behnam Ghavami, Mehrdad Najibi, Hossein Pedram
Issue Date:March 2007
pp. 471-472
In this paper, we present a new efficient methodology for power estimation of QDI Asynchronous circuits at pre-synthesized level. Power estimation at high-level is performed by simulating the intermediate format of the design. This format consists of concu...
 
Verilog HDL, Powered by PLI: a Suitable Framework for Describing and Modeling Asynchronous Circuits at All Levels of Abstraction
Found in: Design Automation Conference
By Arash Saifhashemi, Hossein Pedram
Issue Date:June 2003
pp. 330
In this paper, we show how to use Verilog HDL along with PLI (Programming Language Interface) to model asynchronous circuits at the behavioral level by implementing CSP (Communicating Sequential Processes) language constructs. Channels and communicating ac...
 
Reimbursing the Handshake Overhead of Asynchronous Circuits using Compiler Pre-Synthesis Optimizations
Found in: Digital Systems Design, Euromicro Symposium on
By Sharareh ZamanZadeh, Mohammad Mirza-Aghatabar, Mehrdad Najibi, Hossein Pedram, Abolghasem Sadeghi
Issue Date:September 2008
pp. 290-297
Asynchronous circuits have many advantages vs synchronous design styles like high performance and lower power consumption; however, there is a drawback of big overhead in handshake circuitry of these circuits. In this paper, we have reduced the amount of t...
 
Design and Analysis of a Robust Carbon Nanotube-Based Asynchronous Primitive Circuit
Found in: ACM Journal on Emerging Technologies in Computing Systems (JETC)
By Behnam Ghavami, Hossein Pedram, Mehdi B. Tahoori, Mohsen Raji
Issue Date:February 2013
pp. 1-27
Carbon Nanotube Field Effect Transistors (CNFETs) show great promise as extensions to silicon CMOS. However, CNFET-based circuits will face great fabrication challenges that will translate into important parameter variations and decreased reliability. Henc...
     
Design of dual threshold voltages asynchronous circuits
Found in: Proceeding of the thirteenth international symposium on Low power electronics and design (ISLPED '08)
By Behnam Ghavami, Hossein Pedram
Issue Date:August 2008
pp. 383-384
This paper introduces a framework for the minimization of leakage power consumption of asynchronous circuits via using dual threshold voltages technique. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the c...
     
Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint
Found in: Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI (GLSVLSI '07)
By Hossein Pedram, Kamran Saleh, Mehrdad Najibi
Issue Date:March 2007
pp. 299-304
Asynchronous circuits already have shown their benefits. The main drawback is the lack of powerful CAD and layout generation tools limiting the widespread use of the asynchronous methodology. QDI asynchronous circuits are known as a powerful category of as...
     
An asynchronous fpga logic cell implementation
Found in: Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI (GLSVLSI '07)
By Atabak Mahram, Hossein Pedram, Mehrdad Najibi
Issue Date:March 2007
pp. 176-179
We present a new method for implementing asynchronous FPGA logic cells which are configurable at pipeline level. Previous implementations of the basic elements of these logic cells were based on the pre-charged logic implementation which imposes some limit...
     
Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only)
Found in: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays (FPGA '05)
By Hossein Pedram, Kamran Saleh, Mehdi Sedighi, Mehrdad Najibi, Mohsen Naderi
Issue Date:February 2005
pp. 269-269
This paper introduces a methodology for prototyping Globally Asynchronous Locally Synchronous (GALS) circuits on synchronous commercial FPGAs. A library of required elements for implementing GALS circuits is proposed and general design considerations to su...
     
Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction
Found in: Proceedings of the 40th conference on Design automation (DAC '03)
By Arash Saifhashemi, Hossein Pedram
Issue Date:June 2003
pp. 330-333
In this paper, we show how to use Verilog HDL along with PLI (Programming Language Interface) to model asynchronous circuits at the behavioral level by implementing CSP (Communicating Sequential Processes) language constructs. Channels and communicating ac...
     
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