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Displaying 1-50 out of 86 total
Removing Context Memory from a Multi-context Dynamically Reconfigurable Processor
Found in: 2012 IEEE 6th International Symposium on Embedded Multicore Socs (MCSoC)
By Hideharu Amano,Masayuki Kimura,Nobuaki Ozaki
Issue Date:September 2012
pp. 92-99
Although context memory or configuration cache is a key mechanism for quick dynamicreconfiguration of multi-context Dynamically Reconfigurable Processing Array (DRPA), it requires a large amount of area and energy. In order to save them, methods to remove ...
 
An OpenCL Runtime Library for Embedded Multi-Core Accelerator
Found in: 2012 IEEE 18th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2012)
By Ryuichi Sakamoto,Mikiko Sato,Yusuke Koizumi,Hideharu Amano,Mitaro Namiki
Issue Date:August 2012
pp. 419-422
In recent years, improvements of energy efficiency and computational performance have become a major issue, because smartphones and tablets become popular. To implement high performance, multi-core accelerator consists of general purpose processors and acc...
 
3D NoC with Inductive-Coupling Links for Building-Block SiPs
Found in: IEEE Transactions on Computers
By Yasuhiro Take,Hiroki Matsutani,Daisuke Sasaki,Michihiro Koibuchi,Tadahiro Kuroda,Hideharu Amano
Issue Date:March 2014
pp. 748-763
A wireless 3D NoC architecture is described for building-block SiPs, in which the number of hardware components (or chips) in a package can be changed after chips have been fabricated. The architecture uses inductive-coupling links that can connect more th...
 
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface
Found in: IEEE Micro
By Noriyuki Miura,Yusuke Koizumi,Yasuhiro Take,Hiroki Matsutani,Tadahiro Kuroda,Hideharu Amano,Ryuichi Sakamoto,Mitaro Namiki,Kimiyoshi Usami,Masaaki Kondo,Hiroshi Nakamura
Issue Date:November 2013
pp. 6-15
The authors developed a scalable heterogeneous multicore processor. 3D heterogeneous chip stacking of a general-purpose CPU and reconfigurable multicore accelerators enables various trade-offs between performance and energy consumption. The stacked chips i...
 
An FPGA Implementation of Reconfigurable Real-Time Vision Architecture
Found in: 2013 Workshops of International Conference on Advanced Information Networking and Applications (WAINA)
By Jorge Hiraiwa,Hideharu Amano
Issue Date:March 2013
pp. 150-155
A video processing architecture based on FPGA for real-time embedded vision systems is proposed in this paper. Recently, embedded vision systems are used in various applications. On the other hand, the throughput required to the system has been increasing ...
 
A Circuit Division Method for High-Level Synthesis on Multi-FPGA Systems
Found in: 2013 Workshops of International Conference on Advanced Information Networking and Applications (WAINA)
By Kugami Daiki,Takaaki Miyajima,Hideharu Amano
Issue Date:March 2013
pp. 156-161
High-Level Synthesis has been researched and developed for these 20 years. Not only ASIC, but also reconfigurable devices, especially Field Programmable Gate Array (FPGA) development environment has been improved as well. Various types of large algorithms ...
 
Research of PE Array Connection Network for Cool Mega-Array
Found in: 2013 Workshops of International Conference on Advanced Information Networking and Applications (WAINA)
By Rie Uno,Nobuaki Ozaki,Hideharu Amano
Issue Date:March 2013
pp. 144-149
A Cool Mega Array or CMA is a low power reconfigurable processor array for battery driven mobile devices. We developed a prototype chip CMA-1. It is consisting of the 8 x 8 PE array, micro-controller for controlling data alignment and data memory. We just ...
 
A Domain Specific Language and Toolchain for OpenCV Runtime Binary Acceleration Using GPU
Found in: 2012 Third International Conference on Networking and Computing (ICNC)
By Takaaki Miyajima,David Thomas,Hideharu Amano
Issue Date:December 2012
pp. 175-181
Computationally intensive applications, such as OpenCV, can be off-loaded to accelerators to reduce execution time. However, developing an accelerated system requires a significant amount of time, requiring the developer to first choose an accelerator and ...
   
Castle of Chips: A New Chip Stacking Structure with Wireless Inductive Coupling for Large Scale 3-D Multicore Systems
Found in: 2012 15th International Conference on Network-Based Information Systems (NBiS)
By Hideharu Amano
Issue Date:September 2012
pp. 820-825
The number of stacked chips with wireless inductive coupling interconnect is limited by the physical space for bonding wires of supply voltage. A new chip stacking structure called CoC (Castle on Chips) is proposed for stacking a large number of chips with...
 
Extension of Memory Controller Equipped with MuCCRA-3-DP: Dynamically Reconfigurable Processor Array
Found in: 2012 15th International Conference on Network-Based Information Systems (NBiS)
By Toru Katagiri,Kazuei Hironaka,Hideharu Amano
Issue Date:September 2012
pp. 826-831
In order to achieve a high performance on the Dynamically Reconfigurable Processor Array(DRPA), it is necessary to use PEs effectively. However, a prototype DRPA, MuCCRA-3-DP needs to generate read/write addresses for accessing data memories, and counts a ...
 
Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router
Found in: 2012 IEEE 6th International Symposium on Embedded Multicore Socs (MCSoC)
By Takeo Nakamura,Hiroki Matsutani,Michihiro Koibuchi,Kimiyoshi Usami,Hideharu Amano
Issue Date:September 2012
pp. 59-66
We propose a Multi-Vdd Fine-Grained VariablePipeline (MVFG-VP) router in order to reduce power consumptionof Network-on-Chips (NoCs) designed for many-coreprocessors. MVFG-VP router adjusts its pipeline depth (i.e., communication latency) and supply voltag...
 
Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth
Found in: Reconfigurable Computing and FPGAs, International Conference on
By Kazuei Hironaka,Hideharu Amano
Issue Date:December 2011
pp. 404-409
A coarse grained dynamically reconfigurable processor (CGDRP) with both Dual Vdd and Dual Vth is proposed with power centric Dual Vdd and Dual Vth assignment policies. The evaluation result shows that the Vth and Vdd assignment optimization algorithm reduc...
 
Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects
Found in: International Conference on Natural Computation
By Michihiro Koibuchi,Takafumi Watanabe,Atsushi Minamihata,Masahiro Nakao,Tomoyuki Hiroyasu,Hiroki Matsutani,Hideharu Amano
Issue Date:December 2011
pp. 50-57
Ethernet has been used for interconnection networks of high-performance computing (HPC) systems that include PC clusters. Although a layer-2 Ethernet topology is limited to a tree structure in order to avoid broadcast storms and deadlocks of frames, variou...
 
Vegeta: An Implementation and Evaluation of Development-Support Middleware on Multiple OpenCL Platform
Found in: International Conference on Natural Computation
By Akihiro Shitara,Tetsuya Nakahama,Masahiro Yamada,Toshiaki Kamata,Yuri Nishikawa,Masato Yoshimi,Hideharu Amano
Issue Date:December 2011
pp. 141-147
Programming on the cluster with accelerators like GP-GPU tends to be a mixture of intra-node parallel library based on CUDA or OpenCL and inter-node communication library including MPI. In this work, we proposed, implemented and evaluated VEGETA, a middlew...
 
Proposal of Auto MPI Expansion Tool for Cell Broadband Engine Cluster
Found in: International Conference on Natural Computation
By Tetsuya Nakahama,Masahiro Yamada,Masato Yoshimi,Hideharu Amano
Issue Date:December 2011
pp. 166-172
The productivity of parallel programming has become essential with the rapid advance of multi-core and many-core processors. Especially, the programming environment of economical small or middle scale clusters using accelerators must be improved. Here, a t...
 
Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips
Found in: IEEE Micro
By Nobuaki Ozaki,Yoshihiro Yasuda,Yoshiki Saito,Daisuke Ikebuchi,Masayuki Kimura,Hideharu Amano,Hiroshi Nakamura,Kimiyoshi Usami,Mitaro Namiki,Masaaki Kondo
Issue Date:November 2011
pp. 6-18
Cool Mega-Array (CMA) is an energy-efficient reconfigurable accelerator for battery-driven mobile devices. It has a large processing-element array without memory elements for mapping an application's data-flow graph, a simple programmable microcontroller f...
 
A Dynamic Link-Width Optimization for Network-on-Chip
Found in: Real-Time Computing Systems and Applications, International Workshop on
By Daihan Wang,Michihiro Koibuchi,Tomohiro Yoneda,Hiroki Matsutani,Hideharu Amano
Issue Date:August 2011
pp. 106-108
Network-on-Chip (NoC) is considered to be a promising approach to implement many-core systems and a large number of on-chip router optimization studies have been proposed. In this paper, we propose to dynamically adjust link-width of each port on a router ...
 
SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator
Found in: IEEE Cool Chips
By Nobuaki Ozaki,Kimiyoshi Usami,Hideharu Amano,Mitaro Namiki,Hiroshi Nakamura,Masaaki Kondo
Issue Date:April 2011
pp. 1-3
SLD(Silent Large Datapath)-1 is a prototype accelerator for media processing consisting of a large Processing Element (PE) array which includes 24bit 8 × 8 PEs with combinatorial circuits and a small micro-controller for data memory access. It was fabricat...
 
Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors
Found in: IEEE Transactions on Computers
By Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga
Issue Date:June 2011
pp. 783-799
Multi and many-core applications are sensitive to interprocessor communication latencies, suggesting the need for low-latency on-chip networks. We propose a low-latency router architecture that predicts the output channel to be used by the next packet tran...
 
Reducing instruction TLB's leakage power consumption for embedded processors
Found in: International Conference on Green Computing
By Zhao Lei, Hui Xu, Dasuke Ikebuchi, Hideharu Amano, Tetsuya Sunata, Mitaro Namiki
Issue Date:August 2010
pp. 477-484
This paper presents a leakage efficient instruction TLB (Translation Lookaside Buffer) design for embedded processors. The key observation is that when programs enter a physical page following instructions tend to be fetched from the same page for a rather...
 
Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks
Found in: Networking, Architecture, and Storage, International Conference on
By Jose Miguel Montañana, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano
Issue Date:July 2010
pp. 218-227
Power saving is required for interconnects of modern PC clusters as well as the performance improvement. To reduce the power consumption of switches with maintaining the performance, on/off link regulations that activate and deactivate the links based on t...
 
A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching
Found in: Networking, Architecture, and Storage, International Conference on
By Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano
Issue Date:July 2010
pp. 431-438
System area networks (SANs), which usually employ virtual cut-through switching, have been used to connect hosts in modern PC clusters and massively parallel computers. In this paper, we propose a non-minimal fully adaptive deadlock-free routing mechanism ...
 
Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs
Found in: Networks-on-Chip, International Symposium on
By Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
Issue Date:May 2010
pp. 61-68
This paper proposes an ultra fine-grained run-time power gating of on-chip router, in which power supply to each router component (e.g., VC queue, crossbar MUX, and output latch) can be individually controlled in response to the applied workload.As only th...
 
A Switch-Tagged Routing Methodology for PC Clusters with VLAN Ethernet
Found in: IEEE Transactions on Parallel and Distributed Systems
By Michihiro Koibuchi, Tomohiro Otsuka, Tomohiro Kudoh, Hideharu Amano
Issue Date:February 2011
pp. 217-230
Ethernet has been used for connecting hosts in PC clusters, besides its use in local area networks. Although a layer-2 Ethernet topology is limited to a tree structure because of the need to avoid broadcast storms and deadlocks of frames, various deadlock-...
 
A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGA
Found in: Reconfigurable Computing and FPGAs, International Conference on
By Hideki Yamada, Yasunori Osana, Tomoya Ishimori, Tomonori Ooya, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri
Issue Date:December 2009
pp. 125-130
Mathematical modeling and simulation of cellular systems are important processes in modern life science, to understand the behavior of life as a system. Kinetic model of a biochemical pathways is described as an ordinary differential system, consists of a ...
 
Performance Analysis of ClearSpeed's CSX600 Interconnects
Found in: Parallel and Distributed Processing with Applications, International Symposium on
By Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Akihiro Shitara, Kenichi Miura, Hideharu Amano
Issue Date:August 2009
pp. 203-210
ClearSpeed's CSX600 that consists of 96 Processing Elements (PEs) employs a one-dimensional array topology for a simple SIMD processing. To clearly show the performance factors and practical issues of NoCs in an existing modern many-core SIMD system, this ...
 
An on/off link activation method for low-power ethernet in PC clusters
Found in: Parallel and Distributed Processing Symposium, International
By Michihiro Koibuchi,Tomohiro Otsuka, Hiroki Matsutani,Hideharu Amano
Issue Date:May 2009
pp. 1-11
The power consumption of interconnects is increased as the link bandwidth is improved in PC clusters. In this paper, we propose an on/off link activation method that uses the static analysis of the traffic in order to reduce the power consumption of Ethern...
 
Evaluation of a multicore reconfigurable architecture with variable core sizes
Found in: Parallel and Distributed Processing Symposium, International
By Vu Manh Tuan, Naohiro Katsura, Hiroki Matsutani,Hideharu Amano
Issue Date:May 2009
pp. 1-8
A multicore architecture for processors has emerged as a dominant trend in the chip making industry. As reconfigurable devices gradually prove their capability in improving computation power while preserving flexibility, we are examining a multicore reconf...
 
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression
Found in: VLSI Design, International Conference on
By Kimiyoshi Usami, Toshiaki Shirai, Tasunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura
Issue Date:January 2009
pp. 381-386
This paper describes a design and implementation methodology for fine-grain power gating. Since sleep-in and wakeup are controlled in a fine granularity in run time, shortening the transition time between the sleep and active states is strongly required. I...
 
Design and Implementation of Adaptive Viterbi Decoder for Using A Dynamic Reconfigurable Processor
Found in: Reconfigurable Computing and FPGAs, International Conference on
By Yuken Kishimoto, Shinichiro Haruyama, Hideharu Amano
Issue Date:December 2008
pp. 247-252
Viterbi decoder implemented with hard-wired logic often requires extra cost and consuming power by using individual logic for various constraint length and decode precisions. Although the redundant hardware which is not used in the given condition can be o...
 
Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network
Found in: IEEE Transactions on Parallel and Distributed Systems
By Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano
Issue Date:August 2009
pp. 1126-1141
The topological explorations of on-chip networks are important for efficiently using their enormous wire resources for low-latency and high-throughput communications using a modest silicon budget. In this paper, we propose a novel tree-based interconnectio...
 
Three-Dimensional Layout of On-Chip Tree-Based Networks
Found in: Parallel Architectures, Algorithms, and Networks, International Symposium on
By Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano
Issue Date:May 2008
pp. 281-288
Three-dimensional Network-on-Chip (3-D NoC) is an emerging research area exploring the network architecture of 3-D ICs that stack several smaller wafers or dice for reducing wire length and wire delay. Various network topologies such as meshes, tori, and t...
 
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip
Found in: Networks-on-Chip, International Symposium on
By Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston
Issue Date:April 2008
pp. 13-22
Survival capability is becoming a crucial factor in designing multicore processors built with on-chip packet networks, or networks on chip (NoCs).??In this paper, we propose a lightweight fault-tolerant mechanism for NoCs based on default backup paths (DBP...
 
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
Found in: Networks-on-Chip, International Symposium on
By Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano
Issue Date:April 2008
pp. 23-32
In this paper, we introduce the use of slow-silent virtual channels to reduce the switching power of on-chip networks while keeping the leakage power small. Adding virtual channels to a network improves the throughput until each link bandwidth is saturated...
 
Performance Improvement Methodology for ClearSpeed?s CSX600
Found in: Parallel Processing, International Conference on
By Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano
Issue Date:September 2007
pp. 77
This paper focuses on a performance of network-on-achip (NoC) and I/O of ClearSpeed?s CSX600 coprocessor with 96 multithread processing elements. Two versions of the Himeno Benchmark were implemented on the CSX600 to evaluate its performance when it encoun...
 
Tightly-Coupled Multi-Layer Topologies for 3-D NoCs
Found in: Parallel Processing, International Conference on
By Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
Issue Date:September 2007
pp. 75
Three-dimensional Network-on-Chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for reducing wire length and wire delay. Although the network topology of 3-D NoC has been explored fo...
 
Implementation and Evaluation of a High Speed License Plate Recognition System on an FPGA
Found in: Computer and Information Technology, International Conference on
By Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka
Issue Date:October 2007
pp. 567-572
In order to address some problems on increasing traffic accidents, many researchers have paid attention to active safety techniques using sophisticated image processing like license number recognition. However, it is enough for warning a driver against dan...
 
Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs
Found in: IEEE Transactions on Parallel and Distributed Systems
By Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hiroaki Nishi, Junji Yamamoto, Noboru Tanabe, Tomohiro Kudoh, Hideharu Amano
Issue Date:September 2007
pp. 1282-1295
In this paper, “Martini,” a network interface controller chip for our original network called RHiNET is described. Martini is designed to provide high-bandwidth and low-latency communication with small overhead. To obtain high performan...
 
An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks
Found in: IEEE Transactions on Parallel and Distributed Systems
By Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano
Issue Date:March 2007
pp. 320-333
<p><b>Abstract</b>—System area networks (SANs), which usually accept arbitrary topologies, have been used to connect hosts in PC clusters. Although deadlock-free routing is often employed for low-latency communications using wormhole or v...
 
Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network
Found in: Parallel and Distributed Processing Symposium, International
By Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
Issue Date:March 2007
pp. 81
Fat H-Tree is a novel tree-based interconnection network providing a torus structure, which is formed by combining two folded H-Tree networks, and is an attractive alternative to tree-based networks such as Fat Trees in a microarchitecture domain. In this ...
 
Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet
Found in: Parallel Processing, International Conference on
By Tomohiro Otsuka, Michihiro Koibuchi, Tomohiro Kudoh, Hideharu Amano
Issue Date:August 2006
pp. 479-486
Ethernet has been used for connecting hosts in the area of high performance-per-cost PC clusters. Although L2 Ethernet topology is limited to a tree structure, various routing algorithms on topologies suitable for parallel processing can be employed by app...
 
Hardware Support for MPI in DIMMnet-2 Network Interface
Found in: Innovative Architecture for Future Generation High-Performance Processors and Systems, International Workshop on
By Noboru Tanabe, Akira Kitamura, Tomotaka Miyashiro, Yasuo Miyabe, Takeshi Araki, Zhengzhe Luo, Hironori Nakajo, Hideharu Amano
Issue Date:January 2006
pp. 73-82
In this paper, hardware support for MPI on the DIMMnet-2 network interface plugged into a DDR DIMM slot is presented. This hardware support realize effective eager protocol and effective derived datatype communication of MPI. As a preliminary evaluation, t...
 
Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board
Found in: Parallel and Distributed Computing Applications and Technologies, International Conference on
By Akira Kitamura, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Yoshihiro Hamada, Noboru Tanabe, Hironori Nakajo
Issue Date:December 2005
pp. 778-780
By recent performance improvement of interconnection networks for a PC cluster, standard I/O bus which connects network interface becomes the performance bottleneck. DIMMnet is a network interface which can solve the problem by using the memory bus instead...
 
Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster
Found in: IEEE Transactions on Parallel and Distributed Systems
By Michihiro Koibuchi, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano
Issue Date:August 2005
pp. 747-759
<p><b>Abstract</b>—System Area Networks (SANs), which usually accept arbitrary topologies, have been used to connect nodes in PC/WS clusters or high-performance storage systems. Although deadlock-free routings, multicasts, and topologies ...
 
Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips
Found in: Parallel Processing Workshops, International Conference on
By Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano
Issue Date:June 2005
pp. 273-280
We propose a deterministic routing strategy called flee which introduces non-minimal paths in order to distribute traffic with a high degree of communication locality in Networks-on-Chips. In the recent design methodology, target system and its application...
 
VLAN-Based Minimal Paths in PC Cluster with Ethernet on Mesh and Torus
Found in: Parallel Processing, International Conference on
By Tomohiro Otsuka, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano
Issue Date:June 2005
pp. 567-576
In a PC cluster with Ethernet, well-distributed multiple paths among hosts can be obtained by applying VLAN technology. In this paper, we propose VLAN topology sets and path assignment methods in mesh and torus. The proposed VLAN-based methods on mesh requ...
 
An FPGA-Based, Multi-model Simulation Method for Biochemical Systems
Found in: Parallel and Distributed Processing Symposium, International
By Yasunori Osana, Tomonori Fukushima, Masato Yoshimi, Yow Iwaoka, Yuichiro Shibata, Hiroaki Kitano, Akira Funahashi, Noriko Hiroi, Hideharu Amano
Issue Date:April 2005
pp. 167a
Modeling and simulation of a cellular system on computers are now becoming an essential process in biological researches. However, modern PCs can't provide enough performance to simulate large-scale biochemical networks. ReCSiP is the alternative FPGA-base...
 
Performance and Cost Analysis of Time-Multiplexed Execution on the Dynamically Reconfigurable Processor
Found in: Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
By Hideharu Amano, Shohei Abe, Yohei Hasegawa, Katsuaki Deguchi, Masayasu Suzuki
Issue Date:April 2005
pp. 315-316
Dynamically reconfigurable processors with multi-context facility have been used for various applications. The relationship between context size and performance of such processors is analyzed based on real designs. The Parallelism Diagram which shows the r...
   
Preliminary Evaluation of a FPGA-Based-Prototype of DIMMnet-2 Network Interface
Found in: Innovative Architecture for Future Generation High-Performance Processors and Systems, International Workshop on
By Noboru Tanabe, Akira Kitamura, Tomotaka Miyashiro, Yasuo Miyabe, Tohru Izawa, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano
Issue Date:January 2005
pp. 119-127
Recent performance improvement of interconnection networks for a PC cluster brings a bottleneck in a standard I/O bus such as PCI bus. DIMMnet is a network interface plugged into a memory slot instead of standard I/O buses. This strategy is one of the solu...
 
A New Memory Module for Memory Intensive Applications
Found in: Parallel Computing in Electrical Engineering, International Conference on
By Noboru Tanabe, Hironori Nakajo, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hideharu Amano
Issue Date:September 2004
pp. 123-128
Some applications with gather / scatter operations are difficult to accelerate. These operations cause inefficient cache use in each processor and fine grain global communications in parallel systems. There are several applications with such characteristic...
 
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