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A NUCA Substrate for Flexible CMP Cache Sharing
Found in: IEEE Transactions on Parallel and Distributed Systems
By Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang, Doug Burger, Stephen W. Keckler
Issue Date:August 2007
pp. 1028-1040
<p><b>Abstract</b>—We propose an organization for the on-chip memory system of a chip multiprocessor in which 16 processors share a 16-Mbyte pool of 64 level-2 (L2) cache banks. The L2 cache is organized as a nonuniform cache architecture...
 
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
Found in: Computer Architecture, International Symposium on
By Evan Speight, Hazim Shafi, Lixin Zhang, Ram Rajamony
Issue Date:June 2005
pp. 346-356
<p>With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor cores, varying amounts of level 1 and level 2 caching, and on-chip direc...
 
Raptor: Integrating Checkpoints and Thread Migration for Cluster Management
Found in: Reliable Distributed Systems, IEEE Symposium on
By Hazim Shafi, Evan Speight, John K. Bennett
Issue Date:October 2003
pp. 141
Software distributed shared-memory (SDSM) provides the abstraction necessary to run shared-memory applications on cost-effective parallel platforms such as clusters of workstations. However, problems such as cluster component reliability and cluster manage...
 
An SPU reference model for simulation, random test generation and verification
Found in: Proceedings of the 2006 conference on Asia South Pacific design automation (ASP-DAC '06)
By Balazs Sallay, Brad Michael, Daisuke Hiraoka, Daniel Brokenshire, Gavin Meil, Hazim Shafi, Yukio Watanabe
Issue Date:January 2006
pp. 860-866
An instruction set level reference model was developed for the development of synergistic processing unit (SPU), which is one of the key components of the cell processor [1][2]. This reference model was used for the simulators to define the instruction set...
     
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