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Displaying 1-4 out of 4 total
NIFD: Non-intrusive FPGA Debugger -- Debugging FPGA 'Threads' for Rapid HW/SW Systems Prototyping
International Conference on Field Programmable Logic and Applications
By Hari Angepat, Gage Eads, Christopher Craik, Derek Chiou
Issue Date:September 2010
Debugging hardware has always been difficult when compared to debugging software, in large part due to a lack of convenient visibility. This paper describes the open NIFD framework that provides software-like debugging facilities to both pure FPGA and hybr...
Parallelizing computer system simulators
Parallel and Distributed Processing Symposium, International
By Derek Chiou, Dam Sunwoo, Hari Angepat, Joonsoo Kim, Nikhil A. Patil, William Reinhart, D. Eric Johnson
Issue Date:April 2008
This paper describes NSF-supported work in parallelized computer system simulators being done in the Electrical and Computer Engineering Department at the University of Texas at Austin. Our work is currently following two paths: (i) the FAST simulation met...
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators
Microarchitecture, IEEE/ACM International Symposium on
By Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William Reinhart, Darrel Eric Johnson, Jebediah Keefe, Hari Angepat
Issue Date:December 2007
This paper describes FAST, a novel simulation methodol- ogy that can produce simulators that (i) are orders of mag- nitude faster than comparable simulators, (ii) are cycle- accurate, (iii) model the entire system running unmodified applications and operat...
An FPGA-based In-line Accelerator for Memcached
IEEE Computer Architecture Letters
By maysam lavasani,Hari Angepat,Derek Chiou
Issue Date:July 2013
We present a method for accelerating server applications using a hybrid CPU+FPGA architecture and demonstrate its advantages by accelerating Memcached, a distributed key-value system. The accelerator, implemented on the FPGA fabric, processes request packe...
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