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Displaying 1-22 out of 22 total
Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm
Found in: On-Line Testing Symposium, IEEE International
By Hamid R. Zarandi, Seyed Ghassem Miremadi, Hamid Sarbazi-Azad
Issue Date:July 2004
pp. 101
Data integrity of words coming out of the caches needs to be checked to assure their correctness. This paper proposes a cache placement scheme, which provides high performance as well as high fault detection coverage. In this scheme, the cache space is div...
 
SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs
Found in: Quality Electronic Design, International Symposium on
By Hamid R. Zarandi, Seyed G. Miremadi, Dhiraj K. Pradhan, Jimson Mathew
Issue Date:March 2007
pp. 380-385
In this paper, we propose a new SEU-mitigative placement and routing of circuits in the FPGAs which is based on the popular VPR tool. The VPR tool is modified so that during placement and routing, decisions are taken with awareness of SEU-mitigation. Moreo...
 
A Reliability-Aware Multi-application Mapping Technique in Networks-on-Chip
Found in: 2013 21st Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)
By Fatemeh Khalili,Hamid R. Zarandi
Issue Date:February 2013
pp. 478-485
This paper proposes a reliability-aware mapping technique for multi applications in networks-on-chip. The proposed technique consists of three main steps: 1) Generating a new core graph enriched by spares, based on a given application core graph, 2) Findin...
 
A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAs
Found in: Reconfigurable Computing and FPGAs, International Conference on
By Alireza Rohani, Hamid R. Zarandi
Issue Date:December 2009
pp. 83-88
this paper proposes a new reconfigurable architecture for Configuration Logic Block (CLB) in SRAM-based FPGAs. This architecture can correct Single Event Upset (SEU) by utilizing both Triple Modular Redundancy (TMR) and mapping technique. Since the propose...
 
Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan
Issue Date:September 2007
pp. 340-348
This paper presents a high level method called Matrix code to protect SRAM-based memories against multiple bit upsets. The proposed method combines hamming code and parity code to assure the reliability of memory in presence of multiple bit-upsets with low...
 
A Fault-Tolerant Low-Energy Multi-Application Mapping onto NoC-based Multiprocessors
Found in: 2012 IEEE 15th International Conference on Computational Science and Engineering (CSE)
By Fatemeh Khalili,Hamid R. Zarandi
Issue Date:December 2012
pp. 421-428
This paper proposes a fault-tolerant multi-application mapping technique in NoC-based multiprocessor platforms. The proposed mapping technique is composed of two main parts: 1) Mapping an application core graph to a free non-faulty processing cores, 2) Pla...
 
Susceptibility Analysis of LEON3 Embedded Processor against Multiple Event Transients and Upsets
Found in: 2012 IEEE 15th International Conference on Computational Science and Engineering (CSE)
By Hamed Abbasitabar,Hamid R. Zarandi,Ronak Salamat
Issue Date:December 2012
pp. 548-553
This paper presents an analysis of the effects and propagations of different faults such as Single Event Transient (SET), Multiple Event Transients (MET), Single Event Upset (SEU) and Multiple Bit Upsets (MBU) by simulation-based fault injection into Areof...
 
Low-Cost Software-Implemented Error Detection Technique
Found in: Electronic System Design, International Symposium on
By Mohammad Maghsoudloo,Hamid R. Zarandi,Navid Khoshavi
Issue Date:December 2011
pp. 318-323
In this paper, a software behavior-based technique is presented to detect control-flow error. The analysis of a key point leads to introduce the proposed technique: effective reduction of the overheads of control-flow checking statements through finding th...
 
Soft Error Detection Technique in Multi-threaded Architectures Using Control-Flow Monitoring
Found in: Digital Systems Design, Euromicro Symposium on
By Mohammad Maghsoudloo,Hamid R. Zarandi,Saadat Pour Mozafari,Navid Khoshavi
Issue Date:September 2011
pp. 789-792
This paper presents a software-based error detection technique through monitoring flow of the programs in multithreaded architectures. This technique is based on the analysis of two key ideas: 1) Modifying the structure of traditional control-flow graphs u...
 
Two Efficient Software Techniques to Detect and Correct Control-Flow Errors
Found in: Pacific Rim International Symposium on Dependable Computing, IEEE
By Hamid R. Zarandi, Mohammad Maghsoudloo, Navid Khoshavi
Issue Date:December 2010
pp. 141-148
This paper proposes two efficient software techniques, Control-flow and Data Errors Correction using Data-flow Graph Consideration (CDCC) and Miniaturized Check-Pointing (MCP), to detect and correct control-flow errors. These techniques have been implement...
 
A Probabilistic Method to Detect Anomalies in Embedded Systems
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Mahroo Zandrahimi, Alireza Zarei, Hamid R. Zarandi
Issue Date:October 2010
pp. 152-159
Current-day embedded systems are very vulnerable to faults and defects. Anomaly detection is often the primary means of providing early indication of faults and defects. This paper presents a probabilistic method, which employs the probability of data even...
 
Soft error propagations and effects analysis on CAN controller
Found in: International Conference on Automation, Quality and Testing, Robotics
By Saman Khoshbakht, Hamid R. Zarandi
Issue Date:May 2010
pp. 1-7
This paper presents the evaluation of soft error effects and propagations on a Controller Area Network (CAN) controller using SINJECT fault injection tool. To do this, three main sub-modules of the core were selected for fault injection targets. The experi...
 
An Investigation of Fault Tolerance Behavior of 32-Bit DLX Processor
Found in: Dependability, International Conference on
By Pooria M. Yaghini, Hamid R. Zarandi, Ashkan Eghbal, Akbar Jafarzadeh, Saeedeh Eskandari
Issue Date:June 2009
pp. 93-98
This paper presents a study of fault tolerance behavior of a 32-bit DLX processor. Simulation-based method has been applied to analyze the fault tolerance characteristic of this processor. This experiment is based on injection of 14000 faults among 70 poin...
 
An Analysis of Fault Effects and Propagations in AVR Microcontroller ATmega103(L)
Found in: Availability, Reliability and Security, International Conference on
By Alireza Rohani, Hamid. R. Zarandi
Issue Date:March 2009
pp. 166-172
This paper presents an analysis of the effects and propagations of transient faults by simulation-based fault injection into the AVR microcontroller. This analysis is done by injecting 20000 transient faults into main components of the AVR microcontroller ...
 
Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs
Found in: Parallel and Distributed Processing Symposium, International
By Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan
Issue Date:March 2007
pp. 188
FPGAs are an appealing solution for the space-based remote sensing applications. However, in a low-earth orbit, configuration bits of SRAM-based FPGAs are susceptible to single-event upsets (SEUs). In this paper, a new protected CLB and FPGA architecture a...
 
Investigation of Transient Effects on FPGA-based Embedded Systems
Found in: Embedded Software and Systems, Second International Conference on
By Ali Bakhoda, Seyed Ghassem Miremadi, Hamid R. Zarandi
Issue Date:December 2005
pp. 231-236
In this paper, we present an experimental evaluation of transient effects on an embedded system which uses SRAM-based FPGAs. A total of 7500 transient faults were injected into the target FPGA using Power Supply Disturbances (PSD) and a simple 8-bit microp...
 
Hierarchical Multiple Associative Mapping in Cache Memories
Found in: Engineering of Computer-Based Systems, IEEE International Conference on the
By Hamid R. Zarandi, Seyed Ghassem Miremadi
Issue Date:April 2005
pp. 95-101
In this paper, a new cache placement scheme is proposed to achieve higher hit ratios with respect to the two conventional schemes namely set-associative and direct mapping. Similar to set-associative, in this scheme, cache space is divided into sets of dif...
 
Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs
Found in: Pacific Rim International Symposium on Dependable Computing, IEEE
By Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Alireza Ejlali
Issue Date:March 2004
pp. 327-332
The technology of SRAM-based devices is sensible to Single Event Upsets (SEUs) that may be induced mainly by high energy heavy ions and neutrons. This paper presents a framework for the evaluation of fault-tolerant designs implemented on SRAM-based FPGAs u...
 
Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems
Found in: Parallel and Distributed Computing, International Symposium on
By Hamid R. Zarandi, Seyed Ghassem Miremadi, Alireza Ejlali
Issue Date:October 2003
pp. 281
This paper presents transient and permanent fault injection into Verilog models of digital systems during the design phase by a developed simulation-based fault injection tool called INJECT. With this fault injection tool, it is possible to inject crucial ...
 
Dirty data vulnerability mitigation by means of sharing management in cache coherence protocols
Found in: 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
By Mohammad Maghsoudloo,Hamid R. Zarandi
Issue Date:October 2012
pp. 205-210
In this paper, a comprehensive study is firstly conducted to determine the effects of cache coherence protocols on the characteristics of cache memories in current multi-core processors. The main focus of this study is to analyze the effects of coherence p...
 
Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Hamid R. Zarandi, Seyed Ghassem Miremadi, Alireza Ejlali
Issue Date:November 2003
pp. 485
This paper presents a fault injection tool, called SINJECT that supports several synthesizable and non-synthesizable fault models for dependability analysis of digital systems modeled by popular HDLs. The tool provides injection of transient and permanent ...
 
An efficient, dynamically adaptive method to tolerate transient faults in multi-core systems
Found in: Proceedings of the 13th European Workshop on Dependable Computing (EWDC '11)
By Hamid R. Zarandi, Hananeh Aliee
Issue Date:May 2011
pp. 53-58
This paper presents an adaptive, CPU-aware, fault detection and recovery approach which dynamically modifies the number of replicas in the system. This technique utilizes available unused resources as redundancy. It is transparent for users and does not re...
     
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