Search For:

Displaying 1-10 out of 10 total
Easily Testable Implementation for Bit Parallel Multipliers in GF (2m)
Found in: High-Level Design, Validation, and Test Workshop, IEEE International
By H. Rahaman, J. Mathew, A.M. Jabir, D.K. Pradhan
Issue Date:November 2006
pp. 48-54
A testable implementation of bit parallel multiplier over the finite field GF(2<sup>m</sup>) is proposed. A function independent test set of length (2m+4), which detects all the single stuck-at faults in an m bit GF(2<sup>m</sup>) m...
 
Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m})
Found in: VLSI Test Symposium, IEEE
By H. Rahaman, J. Mathew, B.K. Sikdar, D.K. Pradhan
Issue Date:May 2007
pp. 422-430
This paper presents a C-testable technique for detecting transition faults with 100% fault coverage in the polynomial basis (PB) bit parallel (BP) multiplier circuits over GF(2^{m}). The proposed technique requires only 10 vectors, which is independent of ...
 
Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m)
Found in: VLSI Design, International Conference on
By H. Rahaman, J. Mathew, D. K. Pradhan
Issue Date:January 2007
pp. 479-484
In this paper, a C-testable implementation of polynomial basis (PB) bit parallel (BP) multiplier over the Galois fields of form GF(2m) for detecting stuck-at faults in multiplier circuits has been proposed. The length of the constant test set is only 8. Th...
 
Implementation of Ultra Low-Power 8 Bit CLA Using Single Phase Adiabatic Dynamic Logic
Found in: Advances in Recent Technologies in Communication and Computing, International Conference on
By M. Chanda, S. Naha, S. Manna, A. Dandapat, H. Rahaman
Issue Date:October 2010
pp. 360-364
The paper presents the implementation of ultra low power 8 bit carry look ahead adder circuit operated by single-phase adiabatic dynamic logic (SPADL) which, unlike any other existing adiabatic logic family, uses single sinusoidal supply-clock. This not on...
 
Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set
Found in: On-Line Testing Symposium, IEEE International
By J. Mathew, H. Rahaman, D.K. Pradhan
Issue Date:July 2007
pp. 207-208
We present a C-testable method for detecting stuck-at (s-a) faults in the polynomial basis (PB) bit parallel multiplier circuits over GF(2m). It requires only 7 tests for detecting faults to provide 100% fault coverage, which is independent of the multipli...
   
Cost Optimal Design of Nonlinear CA based PRPG for Test Applications
Found in: Asian Test Symposium
By Sukanta Das, H Rahaman, Biplab K Sikdar
Issue Date:December 2005
pp. 284-287
This paper reports a scheme for cost optimal design of PRPG, built around nonlinear Cellular Automata (CA). The characterization of 3-neighborhood CA rules provides the foundation of designing the n-bit PRPG in linear time. The GA (Genetic Algorithm) frame...
 
Comparative Analysis of Adiabatic Compressor Circuits for Ultra-low Power DSP Application
Found in: Advances in Recent Technologies in Communication and Computing, International Conference on
By M. Chanda, P. Sil, R. Mitra, A. Dandapat, H. Rahaman
Issue Date:October 2010
pp. 355-359
In recent years, a plethora of adiabatic logic styles have been published in literature for ultra low power application, but only very few investigate and compare the performances of these adiabatic logic styles. This paper compares and analyzes the perfor...
 
A Galois Field Based Logic Synthesis Approach with Testability
Found in: VLSI Design, International Conference on
By J. Mathew, H. Rahaman, A.K Singh, A.M. Jabir, D.K Pradhan
Issue Date:January 2008
pp. 629-634
of the most demanding requirements. Efficient testable logic synthesis is one way to tackle the problem. To this end, this paper introduces a new fast efficient graph-based decomposition technique for Boolean functions in finite fields, which utilizes the ...
 
C-testable S-box implementation for secure advanced encryption standard
Found in: On-Line Testing Symposium, IEEE International
By H. Rahaman, J. Mathew, A. Jabir, D. K. Pradhan
Issue Date:June 2009
pp. 210-211
We propose a C-testable S-box implementation which is one of the most complex blocks in AES hardware implementation. Only 12 constant vectors are sufficient to achieve 100% fault coverage in the S-box. C-testability is achieved with an extra hardware overh...
 
Single Error Correcting Finite Field Multipliers Over GF(2<i><sup>m</sup></i>)
Found in: VLSI Design, International Conference on
By Jimson Mathew, A. Costas, A.M. Jabir, H. Rahaman, D.K. Pradhan
Issue Date:January 2008
pp. 33-38
designing single error correcting Galois field multipliers over polynomial basis. The proposed method uses multiple parity prediction circuits to detect and correct logic errors and gives 100% fault coverage both in the functional unit and the parity predi...
 
 1