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Displaying 1-7 out of 7 total
Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example
Found in: 2011 Design, Automation & Test in Europe
By H Hashempour,J Dohmen,Bratislav Tasić,B Kruseman,C Hora,M van Beurden, Yizi Xing
Issue Date:March 2011
pp. 1-6
We present an application of Defect Oriented Testing (DOT 1 ) to an industrial mixed signal device to reduce test time and maintain quality. The device is an automotive IC product with stringent quality requirements and a mature test program that is alread...
   
Compression of VLSI Test Data by Arithmetic Coding
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By H. Hashempour, F. Lombardi
Issue Date:October 2004
pp. 150-157
This paper presents Arithmetic Coding and its application to data compression for VLSI testing. The use of arithmetic codes for compression results in a codeword whose length is close to the optimal value as predicted by entropy in information theory. Prev...
 
Test Time Reduction in a Manufacturing Environment by Combining BIST and ATE
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By H. Hashempour, F. J. Meyer, F. Lombardi
Issue Date:November 2002
pp. 186
This paper analyzes an environment which utilizes Built-In Self-Test (BIST) and Automatic Test Equipment (ATE), to reduce the overall time for manufacturing test of complex digital chips. This requires properly establishing the time to switch from BIST to ...
 
Circuit-Level Modeling and Detection of Metallic Carbon Nanotube Defects in Carbon Nanotube FETs
Found in: Design, Automation and Test in Europe Conference and Exhibition
By H. Hashempour, F. Lombardi
Issue Date:April 2007
pp. 158
Carbon nanotube field effect transistors (CNTFET) are promising nano-scaled devices for implementing high performance, very dense and low power circuits. The core of a CNTFET is a carbon nanotube. Its conductance property is determined by the so-called chi...
 
Hybrid Multisite Testing at Manufacturing
Found in: Test Conference, International
By H. Hashempour, F. J. Meyer, F. Lombardi, F. Karimi
Issue Date:October 2003
pp. 927
This paper deals with Hybrid multisite testing of VLSI chips by utilizing automatic test equipment (ATE) in connection with built-in self-test (BIST). The performance of a multisite testing process is analyzed using device-under-test (DUT) parameters (such...
 
On the Error Effects of Random Clock Shifts in Quantum-dot Cellular Automata Circuits
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By M. Ottavi, H. Hashempour, V. Vankamamidi, F. Karim, K. Walus, A. Ivanov
Issue Date:September 2007
pp. 487-498
This paper analyzes the effect of random phase shifts in the underlying clock signals on the operation of several basic Quantum-dot Cellular Automata (QCA) building blocks. Such phase shifts can result from manufacturing variations or from uneven path leng...
 
Error-Resilient Test Data Compression Using Tunstall Codes
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By H. Hashempour, L. Schiano, F. Lombardi
Issue Date:October 2004
pp. 316-323
This paper presents a novel technique for achieving error-resilience to bit-flips in compressed test data streams. Error-resilience is related to the capability of a test data stream (or sequence) to tolerate bit-flips which may occur in an Automatic Test ...
 
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