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Displaying 1-34 out of 34 total
Shrink-Fit: A Framework for Flexible Accelerator Sizing
Found in: IEEE Computer Architecture Letters
By M. Lyons, Gu-Yeon Wei,D. Brooks
Issue Date:January 2013
pp. 17-20
RTL design complexity discouraged adoption of reconfigurable logic in general purpose systems, impeding opportunities for performance and energy improvements. Recent improvements to HLS compilers simplify RTL design and are easing this barrier. A new chall...
 
Helix: Making the Extraction of Thread-Level Parallelism Mainstream
Found in: IEEE Micro
By Simone Campanoni,Timothy M. Jones,Glenn Holloway,Gu-Yeon Wei,David Brooks
Issue Date:July 2012
pp. 8-18
Improving system performance increasingly depends on exploiting microprocessor parallelism, yet mainstream compilers still don't parallelize code automatically. Helix automatically parallelizes general-purpose programs without requiring any ...
 
Achieving uniform performance and maximizing throughput in the presence of heterogeneity
Found in: High-Performance Computer Architecture, International Symposium on
By Krishna K. Rangan, Michael D. Powell, Gu-Yeon Wei, David Brooks
Issue Date:February 2011
pp. 3-14
Continued scaling of process technologies is critical to sustaining improvements in processor frequencies and performance. However, shrinking process technologies exacerbates process variations -- the deviation of process parameters from their target speci...
 
Voltage Noise in Production Processors
Found in: IEEE Micro
By Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David Brooks
Issue Date:January 2011
pp. 20-28
<p>Voltage variations are a major challenge in processor design. Here, researchers characterize the voltage noise characteristics of programs as they run to completion on a production Core 2 Duo processor. Furthermore, they characterize the implicati...
 
Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David Brooks
Issue Date:December 2010
pp. 77-88
Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel Core2 Duo processor. By sensing on-die ...
 
The Accelerator Store framework for high-performance, low-power accelerator-based systems
Found in: IEEE Computer Architecture Letters
By Michael J. Lyons, Mark Hempstead, Gu-Yeon Wei, David Brooks
Issue Date:July 2010
pp. 53-56
Hardware acceleration can increase performance and reduce energy consumption. To maximize these benefits, accelerator- based systems that emphasize computation on accelerators (rather than on general purpose cores) should be used. We introduce the &#82...
 
Predicting Voltage Droops Using Recurring Program and Microarchitectural Event Activity
Found in: IEEE Micro
By Vijay Janapa Reddi, Meeta Gupta, Glenn Holloway, Michael D. Smith, Gu-Yeon Wei, David Brooks
Issue Date:January 2010
pp. 110-110
<p>Shrinking feature size and diminishing supply voltage are making circuits more sensitive to supply voltage fluctuations within a microprocessor. If left unattended, voltage fluctuations can lead to timing violations or even transistor lifetime iss...
 
Place and route considerations for voltage interpolated designs
Found in: Quality Electronic Design, International Symposium on
By Kevin Brownell, Ali Durlov Khan, David Brooks, Gu-Yeon Wei
Issue Date:March 2009
pp. 594-600
Voltage interpolation is a promising post fabrication technique for combating the effects of process variations. The benefits of voltage interpolation are well understood. Its implementation in a VLSI-CAD flow has been considered through the synthesis stag...
 
Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
Found in: IEEE Micro
By Xiaoyao Liang, Gu-Yeon Wei, David Brooks
Issue Date:January 2009
pp. 127-138
<p>Process variations will significantly degrade the performance benefits of future microprocessors as they move toward nanoscale technology. Device parameter fluctuations can introduce large variations in peak operation among chips, cores on a singl...
 
Evaluation of voltage interpolation to address process variations
Found in: Computer-Aided Design, International Conference on
By Kevin Brownell, Gu-Yeon Wei, David Brooks
Issue Date:November 2008
pp. 529-536
Post-fabrication tuning provides a promising design approach to mitigate the performance and power overheads of process variation in advanced fabrication technologies. This paper explores design considerations and VLSI-CAD support for a recently proposed p...
 
Instruction-driven clock scheduling with glitch mitigation
Found in: Low Power Electronics and Design, International Symposium on
By Gu-Yeon Wei, David Brooks, Ali Durlov Khan, Xiaoyao Liang
Issue Date:August 2008
pp. 357-362
Instruction-driven clock scheduling is a mechanism that minimizes clock power in deeply-pipelined datapaths. Analysis of realistic processor workloads shows a preponderance of bubbles persist through pipelines like the floating point unit. Clock scheduling...
 
Design of low-power short-distance opto-electronic transceiver front-ends with scalable supply voltages and frequencies
Found in: Low Power Electronics and Design, International Symposium on
By Xuning Chen, Gu-Yeon Wei, Li-Shiuan Peh
Issue Date:August 2008
pp. 277-282
The need for low-power I/Os is widely recognized, as I/Os take up a significant portion of total chip power. In recent years, researchers have pointed to the potential system-level power savings that can be realized if dynamic voltage scalable I/Os are ava...
 
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
Found in: Computer Architecture, International Symposium on
By Xiaoyao Liang, Gu-Yeon Wei, David Brooks
Issue Date:June 2008
pp. 191-202
Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introduce large variations in peak operation among chips, among cores on a single chip...
 
Process Variation Tolerant 3T1D-Based Cache Architectures
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks
Issue Date:December 2007
pp. 15-26
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM (6-transistor static memory) structures and will become critical with continu...
 
Towards a software approach to mitigate voltage emergencies
Found in: Low Power Electronics and Design, International Symposium on
By Meeta Sharma Gupta, Krishna K. Rangan, Michael D. Smith, Gu-Yeon Wei, David Brooks
Issue Date:August 2007
pp. 123-128
Increases in peak current draw and reductions in the operating voltages ofprocessors continue to amplify the importance of dealing with voltage fluctuations in processors. One approach suggested has been to not only react to these fluctuations but also att...
 
Understanding Voltage Variations in Chip Multiprocessors using a Distributed Power-Delivery Network
Found in: Design, Automation and Test in Europe Conference and Exhibition
By M.S. Gupta, J.L. Oatley, R. Joseph, Gu-Yeon Wei, D.M. Brooks
Issue Date:April 2007
pp. 119
Recent efforts to address microprocessor power dissipation through aggressive supply voltage scaling and power management require that designers be increasingly cognizant of power supply variations. These variations, primarily due to fast changes in supply...
 
System-on-Chip Architecture Design for Intelligent Sensor Networks
Found in: Intelligent Information Hiding and Multimedia Signal Processing, International Conference on
By Wai-Chi Fang, Sharon Kedar, Susan Owen, Gu-Yeon Wei, David Brooks, Jonathan Lees
Issue Date:December 2006
pp. 579-582
While wireless sensor networks can generically be used for a wide variety of applications, breakthrough innovations are most often achieved when driven by a genuine need or application, with its specific system-level and science-related requirements and ob...
 
An Ultra Low Power System Architecture for Sensor Network Applications
Found in: Computer Architecture, International Symposium on
By Mark Hempstead, Nikhil Tripathi, Patrick Mauro, Gu-Yeon Wei, David Brooks
Issue Date:June 2005
pp. 208-219
Recent years have seen a burgeoning interest in embedded wireless sensor networks with applications ranging from habitat monitoring to medical applications. Wireless sensor networks have several important attributes that require special attention to device...
 
Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems
Found in: High-Performance Computer Architecture, International Symposium on
By Xuning Chen, Li-Shiuan Peh, Gu-Yeon Wei, Yue-Kai Huang, Paul Prucnal
Issue Date:February 2005
pp. 120-131
As microprocessors become increasingly interconnected, the power consumed by the interconnection network can no longer be ignored. Moreover, with demand for link bandwidth increasing, optical links are replacing electrical links in inter-chassis and inter-...
 
Eliminating voltage emergencies via software-guided code transformations
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By David Brooks, Gu-Yeon Wei, Gu-Yeon Wei, Kim Hazelwood, Kim Hazelwood, Meeta S. Gupta, Meeta S. Gupta, Michael D. Smith, Michael D. Smith, Simone Campanoni, Simone Campanoni, Vijay Janapa Reddi, Vijay Janapa Reddi
Issue Date:September 2010
pp. 1-28
In recent years, circuit reliability in modern high-performance processors has become increasingly important. Shrinking feature sizes and diminishing supply voltages have made circuits more sensitive to microprocessor supply voltage fluctuations. These flu...
     
Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures
Found in: 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)
By Yakun Sophia Shao,Brandon Reagen,Gu-Yeon Wei,David Brooks
Issue Date:June 2014
pp. 97-108
Hardware specialization, in the form of accelerators that provide custom datapath and control for specific algorithms and applications, promises impressive performance and energy advantages compared to traditional architectures. Current research in acceler...
   
HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs
Found in: 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)
By Simone Campanoni,Kevin Brownell,Svilen Kanev,Timothy M. Jones,Gu-Yeon Wei,David Brooks
Issue Date:June 2014
pp. 217-228
Data dependences in sequential programs limit parallelization because extracted threads cannot run independently. Although thread-level speculation can avoid the need for precise dependence analysis, communication overheads required to synchronize actual d...
   
Evaluation of voltage stacking for near-threshold multicore computing
Found in: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design (ISLPED '12)
By David Brooks, Gu-Yeon Wei, Sae Kyu Lee
Issue Date:July 2012
pp. 373-378
This paper evaluates voltage stacking in the context of near-threshold multicore computing. Key attributes of voltage stacking are investigated using results from a test-chip prototype built in 150nm FDSOI CMOS. By "stacking" logic blocks on top of each ot...
     
XIOSim: power-performance modeling of mobile x86 cores
Found in: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design (ISLPED '12)
By David Brooks, Gu-Yeon Wei, Svilen Kanev
Issue Date:July 2012
pp. 267-272
Simulation is one of the main vehicles of computer architecture research. In this paper, we present XIOSim - a highly detailed microarchitectural simulator targeted at mobile x86 microprocessors. The simulator execution model that we propose is a blend bet...
     
The accelerator store: A shared memory framework for accelerator-based systems
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By David Brooks, Mark Hempstead, Gu-Yeon Wei, Michael J. Lyons
Issue Date:January 2012
pp. 1-22
This paper presents the many-accelerator architecture, a design approach combining the scalability of homogeneous multi-core architectures and system-on-chip's high performance and power-efficient hardware accelerators. In preparation for systems containin...
     
Tribeca: design for PVT variations with local recovery and fine-grained adaptation
Found in: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (Micro-42)
By David Brooks, Gu-Yeon Wei, Jude A. Rivers, Meeta S. Gupta, Pradip Bose
Issue Date:December 2009
pp. 435-446
With continued advances in CMOS technology, parameter variations are emerging as a major design challenge. Irregularities during the fabrication of a microprocessor and variations of voltage and temperature during its operation widen worst-case timing marg...
     
An accelerator-based wireless sensor network processor in 130nm CMOS
Found in: Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems (CASES '09)
By David Brooks, Gu-Yeon Wei, Mark Hempstead
Issue Date:October 2009
pp. 215-222
Networks of ultra-low-power nodes capable of sensing, computation, and wireless communication have applications in medicine, science, industrial automation, and security. Over the past few years, deployments of wireless sensor networks (WSNs) have utilized...
     
Thread motion: fine-grained power management for multi-core systems
Found in: Proceedings of the 36th annual international symposium on Computer architecture (ISCA '09)
By David Brooks, Gu-Yeon Wei, Krishna K. Rangan
Issue Date:June 2009
pp. 70-73
Dynamic voltage and frequency scaling (DVFS) is a commonly-used power-management scheme that dynamically adjusts power and performance to the time-varying needs of running programs. Unfortunately, conventional DVFS, relying on off-chip regulators, faces li...
     
Instruction-driven clock scheduling with glitch mitigation
Found in: Proceeding of the thirteenth international symposium on Low power electronics and design (ISLPED '08)
By Ali Durlov Khan, David Brooks, Gu-Yeon Wei, Xiaoyao Liang
Issue Date:August 2008
pp. 383-384
Instruction-driven clock scheduling is a mechanism that minimizes clock power in deeply-pipelined datapaths. Analysis of realistic processor workloads shows a preponderance of bubbles persist through pipelines like the floating point unit. Clock scheduling...
     
Design of low-power short-distance opto-electronic transceiver front-ends with scalable supply voltages and frequencies
Found in: Proceeding of the thirteenth international symposium on Low power electronics and design (ISLPED '08)
By Gu-Yeon Wei, Li-Shiuan Peh, Xuning Chen
Issue Date:August 2008
pp. 383-384
The need for low-power I/Os is widely recognized, as I/Os take up a significant portion of total chip power. In recent years, researchers have pointed to the potential system-level power savings that can be realized if dynamic voltage scalable I/Os are ava...
     
Towards a software approach to mitigate voltage emergencies
Found in: Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)
By David Brooks, Gu-Yeon Wei, Krishna K. Rangan, Meeta Sharma Gupta, Michael D. Smith
Issue Date:August 2007
pp. 123-128
Increases in peak current draw and reductions in the operating voltages ofprocessors continue to amplify the importance of dealing with voltage fluctuations in processors. One approach suggested has been to not only react to these fluctuations but also att...
     
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '07)
By David M. Brooks, Gu-Yeon Wei, Meeta S. Gupta, Jarod L. Oatley, Russ Joseph
Issue Date:April 2007
pp. 624-629
Recent efforts to address microprocessor power dissipation through aggressive supply voltage scaling and power management require that designers be increasingly cognizant of power supply variations. These variations, primarily due to fast changes in supply...
     
Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations
Found in: Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems (CASES '06)
By David Brooks, Gu-Yeon Wei, Mark Hempstead
Issue Date:October 2006
pp. 368-378
Rising interest in the applications of wireless sensor networks has spurred research in the development of computing systems for low-throughput, energy-constrained applications. Unlike traditional performance oriented applications, sensor network nodes are...
     
Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack
Found in: Proceedings of the 46th Annual Design Automation Conference (DAC '09)
By David Brooks, Gu-yeon Wei, Meeta S. Gupta, Michael D. Smith, Simone Campanoni, Vijay Janapa Reddi
Issue Date:July 2009
pp. 788-793
Power constrained designs are becoming increasingly sensitive to supply voltage noise. We propose a hardware-software collaborative approach to enable aggressive operating margins: a checkpoint-recovery mechanism corrects margin violations, while a run-tim...
     
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