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Mapping N-Port Memory with Dual-Port Array
Found in: Computer Science and Information Engineering, World Congress on
By Gu Yijun, Wang Zuo
Issue Date:April 2009
pp. 444-447
It has become clear that on-chip storage is criticalfor most applications on FPGAs. In order to utilize onchip storage efficiently, scholars have done some researches on implementing user memory models with embedded single-port and dual-port arrays. Their ...
 
A Hierarchical Architecture of N-Port Memory Based on FPGA
Found in: Convergence Information Technology, International Conference on
By Wang Zuo,Gu Yijun
Issue Date:November 2007
pp. 157-161
As FPGAs grow in logic capacity, they are being used to implement entire systems which require large amount of storage. Most commercial devices implement on-chip storage by providing several large arrays embedded into the FPGA. Scholars have done some rese...
 
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