Search For:

Displaying 1-50 out of 56 total
Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS
Found in: Design and Diagnostics of Electronic Circuits and Systems
By Georges Gielen
Issue Date:April 2009
pp. 1
With the advanced scaling of CMOS technology in the nanometer range, highly integrated mixed-signal systems can be designed. The use of nanometer CMOS, however, poses many challenges. This keynote presentation gives an overview of problems due to increased...
   
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Georges Gielen, Wim Dehaene, Phillip Christie, Dieter Draxelmayr, Edmond Janssens, Karen Maex, Ted Vucurevich
Issue Date:March 2005
pp. 36-42
This special session adresses the problems that designers face when implementing analog and digital circuits in nanometer technologies. An introductory embedded tutorial will give an overview of the design problems at hand : the leakage power and process v...
 
An Efficient Optimization-based Technique to Generate Posynomial Performance Models for Analog Integrated Circuits
Found in: Design Automation Conference
By Walter Daems, Georges Gielen, Willy Sansen
Issue Date:June 2002
pp. 431
This paper presents an new direct-fitting method to generate posynomial response surface models with arbitrary constant exponents for linear and nonlinear performance parameters of analog integrated circuits. Posynomial models enable the use of efficient g...
 
Simulation-based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing
Found in: Computer-Aided Design, International Conference on
By Walter Daems, Georges Gielen, Willy Sansen
Issue Date:November 2001
pp. 70
This paper presents a method to automatically generate posynomial response surface models for the performance parameters of analog integrated circuits. The posynomial models enable the use of efficient geometric programming techniques for circuit sizing an...
 
A Behavioral Signal Path Modeling Methodology for Qualitative Insight in and Efficient Sizing of CMOS Opamps
Found in: Computer-Aided Design, International Conference on
By Francky Leyn, Walter Daems, Georges Gielen, Willy Sansen
Issue Date:November 1997
pp. 374
This paper describes a new modeling methodology that allows to derive systematically behavioral signal path models of operational amplifiers. Combined with symbolic simulation, these models provide high qualitative insight in the small-signal functioning o...
 
Efficient analytical macromodeling of large analog circuits by Transfer Function Trajectories
Found in: Computer-Aided Design, International Conference on
By Dimitri De Jonghe,Georges Gielen
Issue Date:November 2011
pp. 91-94
Automated abstraction of large analog circuits greatly improves simulation time in custom analog design flows. Due to the high degree of variety of circuits this task is mainly a manual ad-hoc approach. This paper proposes an automated modeling approach fo...
 
A methodology for measuring transistor ageing effects towards accurate reliability simulation
Found in: On-Line Testing Symposium, IEEE International
By Elie Maricau, Georges Gielen
Issue Date:June 2009
pp. 21-26
Emerging die-level stress effects (i.e. NBTI, HCI, TDDB, etc.) in nanometer CMOS technologies cause both analog and digital circuit parameters to degrade over time. To efficiently evaluate these degradation effects in modern ICs, a reliability simulator, u...
 
Importance sampled circuit learning ensembles for robust analog IC design
Found in: Computer-Aided Design, International Conference on
By Peng Gao, Trent McConaghy, Georges Gielen
Issue Date:November 2008
pp. 396-399
This paper presents ISCLEs, a novel and robust analog design method that promises to scale with Moore’s Law, by doing boosting-style importance sampling on digital-sized circuits to achieve the target analog behavior. ISCLEs consists of: (1) a boosting alg...
 
Automated extraction of expert knowledge in analog topology selection and sizing
Found in: Computer-Aided Design, International Conference on
By Trent McConaghy, Pieter Palmers, Georges Gielen, Michiel Steyaert
Issue Date:November 2008
pp. 392-395
This paper presents a methodology for analog designers to maintain their insights into the relationship among performance specifications, topology choice, and sizing variables, despite those insights being constantly challenged by changing process nodes an...
 
CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Trent McConaghy, Tom Eeckelaert, Georges Gielen
Issue Date:March 2005
pp. 1082-1087
This paper presents a method to automatically generate compact symbolic performance models of analog circuits with no prior specification of an equation template. The approach takes SPICE simulation data as input, which enables modeling of any nonlinear ci...
 
Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Tom Eeckelaert, Trent McConaghy, Georges Gielen
Issue Date:March 2005
pp. 1070-1075
An efficient methodology is presented to generate the Pareto-optimal hypersurface of the performance space of a complete mixed-signal electronic system. This Pareto-optimal front offers the designer access to all optimal design solutions: starting from the...
 
Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Ewout Martens, Georges Gielen
Issue Date:March 2005
pp. 120-125
This paper presents a novel method for simulation of sampled systems with weakly nonlinear behavior. These systems can be characterized by adding weakly nonlinear terms to the linear state-space equations of the system resulting in an extended state-space ...
 
A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Ewout Martens, Georges Gielen
Issue Date:February 2004
pp. 10436
A novel approach for the modeling of front-end architectures is presented. Architectures are described as a system transforming polyphase harmonic signals through building blocks modeled by polyphase harmonic transfer matrices and distortion tensors. The m...
 
Digital Ground Bounce Reduction by Phase Modulation of the Clock
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges Gielen, Hugo De Man
Issue Date:February 2004
pp. 10088
The digital switching noise that propagates through the chip substrate to the analog circuitry on the same chip is a major limitation for mixed-signal SoC integration. In synchronous digital systems, digital circuits switch simultaneously on the clock edge...
 
High-Level Modeling of Continuous-Time ∆Σ A/D-Converters Using Formal Models
Found in: Asia and South Pacific Design Automation Conference
By Ewout Martens, Georges Gielen
Issue Date:January 2004
pp. 51-56
Increasing complexity of modern mixed-signal chips requires systematic analysis and design methodologies High-level formal models are a key ingredient for the high-level synthesis of systems-on-chip. This paper proposes a formal description of continuous-t...
 
A Generalized Method for Computing Oscillator Phase Noise Spectra
Found in: Computer-Aided Design, International Conference on
By Piet Vanassche, Georges Gielen, Willy Sansen
Issue Date:November 2003
pp. 247
This paper presents a generalized semi-analytic method for computing oscillator phase noise spectra, including the details very close to the oscillation frequency. The starting point is a general relation between an oscillator's output power spectral densi...
 
Architectural Selection of A/D Converters
Found in: Design Automation Conference
By Martin Vogels, Georges Gielen
Issue Date:June 2003
pp. 974
A method for the architectural selection of analog to digital (A/D) converters based on a generic figure of merit is described. First a figure of merit for the power consumption is introduced. This figure of merit includes both target specifications and te...
 
A Model of Computation for Continuous-Time Δ-Σ Modulators
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Ewout Martens, Georges Gielen
Issue Date:March 2003
pp. 10162
In this paper a formal model of computation is proposed to perform time-efficient simulations of continuous-time ΔΣ modulators. It is based on the state-space representation of the modulator. The formal character of the model makes it suited for implementa...
 
Figure of Merit Based Selection of A/D Converters
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Martin Vogels, Georges Gielen
Issue Date:March 2003
pp. 11090
A new method for selecting analog to digital (A/D) converters based on a generic figure of merit is described. First a figure of merit is introduced that includes both specifications and technology data and that has five generic parameters. The values of t...
   
Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Wolfgang Eberle, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Georges Gielen, Hugo De Man
Issue Date:March 2003
pp. 10642
Wireless LAN (WLAN) operating in the 5-6 GHz range, become commercially viable only, if they can be produced at low cost. Consequently, tight integration of the physical layer, consisting of the radio front-end and the digital signal processing part, is a ...
 
Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Piet Vanassche, Georges Gielen, Willy Sansen
Issue Date:March 2003
pp. 10238
This paper presents a new, frequency-domain based method for modeling and analysis of phase-locked loop (PLL) small-signal behavior, including time-varying aspects. Focus is given to PLLs with sampling phase-frequency detectors (PFDs) which compute the pha...
 
HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Bart De Smedt, Georges Gielen
Issue Date:March 2003
pp. 10256
A novel methodology is presented to structured yield-aware synthesis. The trade-off between yield and the unspecified performances is explored along the design space boundaries, while respecting specifications on the other performances. Through the unique ...
 
Generalized Posynomial Performance Modeling
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Tom Eeckelaert, Walter Daems, Georges Gielen, Willy Sansen
Issue Date:March 2003
pp. 10250
This paper presents a new method to automatically generate posynomial symbolic expressions for the performance characteristics of analog integrated circuits. The coefficient set as well as the exponent set of the posynomial expression are determined based ...
 
On the difference between two widely publicized methods for analyzing oscillator phase behavior
Found in: Computer-Aided Design, International Conference on
By Willy Sansen, Georges Gielen, Piet Vanassche
Issue Date:November 2002
pp. 229-233
This paper describes the similarities and differences between two widely publicized methods for analyzing oscillator phase behavior. The methods were presented in [3] and [6]. It is pointed out that both methods are almost alike. While the one in [3] can b...
 
Clock Tree Optimization in Synchronous CMOS Digital Circuits for Substrate Noise Reduction Using Folding of Supply Current Transients
Found in: Design Automation Conference
By Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Ingrid Verbauwhede, Georges Gielen, Hugo De Man
Issue Date:June 2002
pp. 399
In a synchronous clock distribution network with zero latencies, digital circuits switch simultaneously on the clock edge, therefore they generate substrate noise due to the sharp peaks on the supply current. We present a novel methodology optimizing the c...
 
Behavioral Modeling of (Coupled) Harmonic Oscillators
Found in: Design Automation Conference
By Piet Vanassche, Georges Gielen, Willy Sansen
Issue Date:June 2002
pp. 536
A new approach is presented for the construction of behavioral models for harmonic oscillators and sets of coupled harmonic oscillators. The models can be used for system-level simulations and trade-off analysis. Besides the steady-state behavior, the mode...
 
Optimal Design of Delta-Sigma ADCs by Design Space Exploration
Found in: Design Automation Conference
By Ovidiu Bajdechi, Georges Gielen, Johan H. Huijsing
Issue Date:June 2002
pp. 443
An algorithm for architecture-level exploration of ∆Σ ADC design space is presented. The algorithm finds an optimal solution by exhaustively exploring both single-loop and cascaded architectures, with single-bit or multi-bit quantizer, for a range of overs...
 
Efficient DDD-Based Symbolic Analysis of Large Linear Analog Circuits
Found in: Design Automation Conference
By Georges Gielen, Wim Verhaegen
Issue Date:June 2001
pp. 139-144
A new technique for generating approaximate symbolic expressions for network functions in linear(ized) analog circuits is presented. It is based on the compact determinant decision diagram (DDD) representation of the circuit. An implementation of a term ge...
 
High-Level Simulation of Substrate Noise Generation from Large Digital Circuits with Multiple Supplies
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Mustafa Badaroglu, K.U. Leuven, Marc Van Heijningen, Vincent Gravot, Stéphane Donnay, Hugo de Man, Marc Engels, Ivo Bolsens, Georges Gielen
Issue Date:March 2001
pp. 0326
Abstract: Substrate noise generated by large digital circuits degrades the performance of analog circuits sharing the same substrate. Existing approaches usually extract the model of the substrate from the layout information and then simulate the extracted...
 
Efficient Time-Domain Simulation of Telecom Frontends Using a Complex Damped Exponential Signal Model
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Piet Vanassche, Georges Gielen, Willy Sansen
Issue Date:March 2001
pp. 0169
Abstract: This paper presents an efficient time-domain simulation approach for telecommunication frontends at architectural level. It is based upon the use of complex damped exponential modeling functions. These allow to construct accurate signal models fo...
 
ACTIF: A high-level power estimation tool for Analog Continuous-Time Filters
Found in: Computer-Aided Design, International Conference on
By Erik Lauwers, Georges Gielen
Issue Date:November 2000
pp. 193
A tool is presented that gives a high-level estimation of the power consumed by an analog continuous-time OTA-C filter when given only high-level input parameters such as dynamic range and signal swing. When used in combination with estimators for other bu...
 
High-Level Design Case of a Switched-Capacitor Low-Pass Filter Using Verilog-A
Found in: Behavioral Modeling and Simulation, IEEE/ACM International Workshop on
By Erik Lauwers, Georges Gielen, Koen Lampaert, Paolo Miliozzi
Issue Date:October 2000
pp. 16
System design requires experienced designers that use heuristics and built up knowledge to propose a high order solution. Behavioral models can help to formalize, optimise and speed up this design cycle. A design case is presented that shows how behavioral...
 
Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits
Found in: Design Automation Conference
By Walter Daems, Georges Gielen, Willy Sansen
Issue Date:June 1999
pp. 958-963
This paper presents a method to reduce the complexity of a linear or linearized (small-signal) analog circuit. The reduction technique, based on quality-error ranking, can be used as a standard reduction engine that ensures the validity of the resulting ne...
 
A High-Level Design and Optimization Tool for Analog RF Receiver Front-Ends
Found in: Computer-Aided Design, International Conference on
By Jan Crols, Steaphane Donnay, Michiel Steyaert, Georges Gielen
Issue Date:November 1995
pp. 0550
This paper presents a high-level analysis and optimization tool for the design of analog RF receiver front-ends, which takes all design parameters and all aspects of performance degradation (noise, distortion, self-mixing.) into account. The simulations ar...
 
CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design
Found in: Computer-Aided Design, International Conference on
By Domine Leenaerts, Georges Gielen, Rob A. Rutenbar
Issue Date:November 2001
pp. 270
This tutorial paper addresses the problems and solutions that are posed by the design of mixed-signal integrated systems on chip (SoC). These include problems in mixed-signal design methodologies and flows, problems in analog design productivity, as well a...
 
Efficient Analog Circuit Synthesis with simultaneous Yield and Robustness Optimization
Found in: Computer-Aided Design, International Conference on
By Georges Gielen, Geert Debyser
Issue Date:November 1998
pp. 308-311
The paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The starting point of this methodology is a declarative analytical description of t...
 
An Efficient DC Root Solving Algorithm with Guaranteed Convergence for Analog Integrated CMOS Circuits
Found in: Computer-Aided Design, International Conference on
By Willy Sansen, Georges Gielen, Franky Leyn
Issue Date:November 1998
pp. 304-307
The paper describes a new DC modeling methodology applicable to CMOS integrated circuits. It is named operating point driven DC formulation because the operating point is specified directly, and the device dimensions W and L are determined out of it. With ...
 
Guess, solder, measure, repeat: how do I get my mixed-signal chip right?
Found in: Proceedings of the 46th Annual Design Automation Conference (DAC '09)
By Andreas Kuehlmann, Eric Grimme, Geoffrey Ying, George Gielen, Ken Kundert, Martin O'Leary, Sandeep Tare, Warren Wong
Issue Date:July 2009
pp. 520-521
Over the past 20 years, EDA has developed a solid digital implementation methodology that combines some restrictions on the design style with a set of comprehensive tools leading to predictable design flows. The recent increased use of analog components in...
     
Simultaneous multi-topology multi-objective sizing across thousands of analog circuit topologies
Found in: Proceedings of the 44th annual conference on Design automation (DAC '07)
By Georges Gielen, Michiel Steyaert, Pieter Palmers, Trent McConaghy
Issue Date:June 2007
pp. 944-947
This paper presents MOJITO, a system which optimizes across thousands of analog circuit topologies simultaneously, and returns a set of sized topologies that collectively provide a performance tradeoff. MOJITO defines a space of possible topologies as a hi...
     
An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '07)
By Georges Gielen, Michiel Steyaert, Raf Schoofs, Tom Eeckelaert, Willy Sansen
Issue Date:April 2007
pp. 81-86
An hierarchical synthesis methodology for analog and mixed-signal systems is presented that fully in a novel way integrates topology selection at all levels. A hierarchical system optimizer takes multiple topologies for all the building blocks at each hier...
     
Automation in mixed-signal design: challenges and solutions in the wake of the nano era
Found in: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design (ICCAD '06)
By Georges Gielen, Trent McConaghy
Issue Date:November 2006
pp. 461-463
The use of CMOS nanometer technologies at 65 nm and below will pose serious challenges on the design of mixed-signal integrated systems in the very near future. Rising design complexities, tightening time-to-market constraints, leakage power, increasing te...
     
Hierarchical bottom--up analog optimization methodology validated by a delta--sigma A/D converter design for the 802.11a/b/g standard
Found in: Proceedings of the 43rd annual conference on Design automation (DAC '06)
By Georges Gielen, Michiel Steyaert, Raf Schoofs, Tom Eeckelaert, Willy Sansen
Issue Date:July 2006
pp. 25-30
This paper describes key points and experimental validation in the development of a bottom--up hierarchical, multi--objective evolutionary design methodology for analog blocks. The methodology is applied to a continuous--time ΔΣ A/D converter for...
     
Canonical form functions as a simple means for genetic programming to evolve human-interpretable functions
Found in: Proceedings of the 8th annual conference on Genetic and evolutionary computation (GECCO '06)
By Georges Gielen, Trent McConaghy
Issue Date:July 2006
pp. 855-862
In this paper, we investigate the use of canonical form functions to evolve human-interpretable expressions for symbolic regression problems. The approach is simple to apply, being mostly a grammar that fits into any grammar-based Genetic Programming (GP) ...
     
Performance space modeling for hierarchical synthesis of analog integrated circuits
Found in: Proceedings of the 42nd annual conference on Design automation (DAC '05)
By Georges Gielen, Tom Eeckelaert, Trent McConaghy
Issue Date:June 2005
pp. 881-886
Automated analog sizing is becoming an unavoidable solution for increasing analog design productivity. The complexity of typical analog SoC subsystems however calls for efficient methods that can handle design hierarchy, in terms of both performance estima...
     
Architectural selection of A/D converters
Found in: Proceedings of the 40th conference on Design automation (DAC '03)
By Georges Gielen, Martin Vogels
Issue Date:June 2003
pp. 974-977
A method for the architectural selection of analog to digital (A/D) converters based on a generic figure of merit is described. First a figure of merit for the power consumption is introduced. This figure of merit includes both target specifications and te...
     
On the difference between two widely publicized methods for analyzing oscillator phase behavior
Found in: Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design (ICCAD '02)
By Georges Gielen, Piet Vanassche, Willy Sansen
Issue Date:November 2002
pp. 229-233
This paper describes the similarities and differences between two widely publicized methods for analyzing oscillator phase behavior. The methods were presented in [3] and [6]. It is pointed out that both methods are almost alike. While the one in [3] can b...
     
Behavioral modeling of (coupled) harmonic oscillators
Found in: Proceedings of the 39th conference on Design automation (DAC '02)
By Georges Gielen, Piet Vanassche, Willy Sansen
Issue Date:June 2002
pp. 536-541
A new approach is presented for the construction of behavioral models for harmonic oscillators and sets of coupled harmonic oscillators. The models can be used for system-level simulations and trade-off analysis. Besides the steady state behavior, the mode...
     
Optimal design of delta-sigma ADCs by design space exploration
Found in: Proceedings of the 39th conference on Design automation (DAC '02)
By Georges Gielen, Johan H. Huijsing, Ovidiu Bajdechi
Issue Date:June 2002
pp. 443-448
An algorithm for architecture-level exploration of &SGR;D ADC design space is presented. The algorithm finds an optimal solution by exhaustively exploring both single-loop and cascaded architectures, with single-bit or multi-bit quantizer, for a range of o...
     
An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits
Found in: Proceedings of the 39th conference on Design automation (DAC '02)
By Georges Gielen, Walter Daems, Willy Sansen
Issue Date:June 2002
pp. 431-436
This paper presents an new direct--fitting method to generate posynomial response surface models with arbitrary constant exponents for linear and nonlinear performance parameters of analog integrated circuits. Posynomial models enable the use of efficient ...
     
Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients
Found in: Proceedings of the 39th conference on Design automation (DAC '02)
By Georges Gielen, Hugo De Man, Ingrid Verbauwhede, Kris Tiri, Mustafa Badaroglu, Piet Wambacq, StEphane Donnay
Issue Date:June 2002
pp. 399-404
In a synchronous clock distribution network with zero latencies, digital circuits switch simultaneously on the clock edge, therefore they generate substrate noise due to the sharp peaks on the supply current. We present a novel methodology optimizing the c...
     
 1  2 Next >>