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Displaying 1-14 out of 14 total
Failure Tests on 64 Mb SDRAM in Radiation Environment
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By S. Bertazzoni, G.C. Cardarilli, D. Piergentili, M. Salmeri, A. Salsano, D. Di Giovenale, G.C. Grande, P. Marinucci, S. Sperandei, S. Bartalucci, G. Mazzenga, M. Ricci, V. Bidoli, D. de Francesco, P.G. Picozza, A. Rovelli
Issue Date:November 1999
pp. 158
In this paper we analyze the failures of Commercial Off The Shelf (COTS) 64 Mb Synchronous DRAM in radiation environment. The experimental setup, the test procedure, and the results of three different test runs at the Catania LNS-INFN cyclotron are describ...
 
Localization of Faults in Radix-n Signed Digit Adders
Found in: On-Line Testing Symposium, IEEE International
By G.C. Cardarilli, M. Ottavi, S. Pontarelli,, M. Re, A. Salsano
Issue Date:July 2006
pp. 178-180
It is widely known that a adder can be checked by using check symbols that are residues of the numbers modulo some base. This paper extends this characteristic to a radix r Signed Digit (SD) representation. The confinement of the carry operation can also b...
 
A Fault-Tolerant 176 Gbit Solid State Mass Memory Architecture
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By G.C. Cardarilli, A. Salsano, P. Marinucci, M. Ottavi
Issue Date:October 2000
pp. 173
This paper presents a new Solid State Mass Memory (SSMM) suitable for space applications. Using two different approaches increases the memory reliability. Firstly, memory mass fault-tolerance, with respect to hard failures, is obtained by using a fine-gran...
 
Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders
Found in: On-Line Testing Symposium, IEEE International
By S. Pontarelli, L. Sterpone, G.C. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante
Issue Date:July 2007
pp. 194-196
This paper shows how the use of exhaustive fault injection campaigns in conjunction with the analysis of the property of a circuit, allows to improve the efficiency of the checker of self checking circuits. Experimental results coming from fault injection ...
 
Error Correction Codes for SEU and SEFI Tolerant Memory Systems
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By S. Pontarelli, G.C. Cardarilli, M. Re, A. Salsano
Issue Date:October 2009
pp. 425-430
In this paper a modification of the Hsiao SEC-DED (Single Error Correction, Double Error Detection) code is presented. The proposed code is still a SEC-DED code, but it is also able to correct a byte erasure. This code has been developed to protect the mem...
 
Error detection in addition chain based ECC Point Multiplication
Found in: On-Line Testing Symposium, IEEE International
By S. Pontarelli, G.C. Cardarilli, M. Re, A. Salsano
Issue Date:June 2009
pp. 192-194
In this paper the problem of error detection in elliptic curve point multiplication is faced. Elliptic Curve Point Multiplication is often used to design cryptographic algorithms that use fewer bits than other methods with the same security level. One of t...
 
A Novel Error Detection and Correction Technique for RNS Based FIR Filters
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By S. Pontarelli, G.C. Cardarilli, M. Re, A. Salsano
Issue Date:October 2008
pp. 436-444
n this paper a novel technique for detecting and correcting errors in the RNS representation is presented. It is based on the selection of a particular subset of the legitimate range of the RNS representation characterized by the property that each element...
 
Totally Fault Tolerant RNS Based FIR Filters
Found in: On-Line Testing Symposium, IEEE International
By S. Pontarelli, G.C. Cardarilli, M. Re, A. Salsano
Issue Date:July 2008
pp. 192-194
In this paper, the design of a Finite Impulse Response (FIR) filter with fault tolerant capabilities based on the residue number system is analyzed. Differently from other approaches that use RNS, the filter implementation is fault tolerant not only with r...
 
Optimization of Self Checking FIR filters by means of Fault Injection Analysis
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By S. Pontarelli, L. Sterpone, G.C. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante
Issue Date:September 2007
pp. 96-104
In this paper the design of a FIR filter with self checking capabilities based on the residue checking is analyzed. Usually the set of residues used to check the consistency of the results of the FIR filter are based of theoretic considerations about the d...
 
FPGA oriented design of parity sharing RS codecs
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By G.C. Cardarilli, S. Pontarelli, M. Re, A. Salsano
Issue Date:October 2005
pp. 259-265
<p>Reed Solomon codes are widely used to protect the information from errors in transmission and storage systems. RS codes rely on arithmetic in finite, or Galois fields. Most of the RS coders are based on the field GF(28), using a byte as a symbol a...
 
A Self Checking Reed Solomon Encoder: Design and Analysis
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By G.C. Cardarilli, S. Pontarelli, M. Re, A. Salsano
Issue Date:October 2005
pp. 111-119
<p>Reed Solomon codes are widely used to identify and correct data errors in transmission and storage systems. Due to the vital importance of these blocks, a very important research topic is the study of the effects of faults on their behavior. The p...
 
System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By S. Pontarelli, G.C. Cardarilli, A. Malvoni, M. Ottavi, M. Re, A. Salsano
Issue Date:October 2001
pp. 0455
This paper presents a design methodology for fault tolerant sequential systems implemented on System on Chip (SoC). In the paper, as an example, a complex fault tolerant finite state machine has been mapped on the FPGA contained in the SoC. The fault ident...
 
Design of Fault-Tolerant Solid State Mass Memory
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By G.C. Cardarilli, S. Bertazzoni, M. Salmeri, A. Salsano, P. Marinucci
Issue Date:November 1999
pp. 302
This paper presents the flow used for the design of a fault-tolerant Solid State Mass Memory (SSMM) based on Commercial Off The Shelf (COTS) 64 Mb DRAMs. The effects of high-energy radiation on these devices are often complex.In particular, we consider hea...
 
Error Detection in Signed Digit Arithmetic Circuit with Parity Checker
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By G.C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, A. Salsano
Issue Date:November 2003
pp. 401
This paper proposes a methodology for the development of simple arithmetic self-checking circuits using Signed Digit representation. In particular, the architecture of an adder is reported and its self-checking capability with respect to the stuck-at fault...
 
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