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Displaying 1-29 out of 29 total
Embedded Intelligent SRAM
Found in: Design Automation Conference
By Prabhat Jain, G. Edward Suh, Srinivas Devadas
Issue Date:June 2003
pp. 869
Many embedded systems use a simple pipelined RISC processor for computation and an on-chip SRAM for data storage. We present an enhancement called Intelligent SRAM (ISRAM) that consists of a small computation unit with an accumulator that is placed near th...
 
Aegis: A Single-Chip Secure Processor
Found in: IEEE Design and Test of Computers
By G. Edward Suh, Charles W. O'Donnell, Srinivas Devadas
Issue Date:November 2007
pp. 570-580
This article presents the Aegis secure processor architecture, which enables physically secure computing platforms with a main processor as the only trusted component. The Aegis architecture ensures private and authentic program execution even in the face ...
 
Static virtual channel allocation in oblivious routing
Found in: Networks-on-Chip, International Symposium on
By Keun Sup Shim, Myong Hyon Cho, Michel Kinsy, Tina Wen, Mieszko Lis, G. Edward Suh, Srinivas Devadas
Issue Date:May 2009
pp. 38-43
Most virtual channel routers have multiple virtual channels to mitigate the effects of head-of-line blocking. When there are more flows than virtual channels at a link, packets or flows must compete for channels, either in a dynamic way at each link or by ...
 
Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions
Found in: Computer Architecture, International Symposium on
By G. Edward Suh, Charles W. O'Donnell, Ishan Sachdev, Srinivas Devadas
Issue Date:June 2005
pp. 25-36
Secure processors enable new applications by ensuring private and authentic program execution even in the face of physical attack. In this paper we present the AEGIS secure processor architecture, and evaluate its RTL implementation on FPGAs. By using Phys...
 
Optimal and Heuristic Application-Aware Oblivious Routing
Found in: IEEE Transactions on Computers
By Michel A. Kinsy,Myong Hyon Cho,Keun Sup Shim,Mieszko Lis,G. Edward Suh,Srinivas Devadas
Issue Date:January 2013
pp. 59-73
Conventional oblivious routing algorithms do not take into account resource requirements (e.g., bandwidth, latency) of various flows in a given application. As they are not aware of flow demands that are specific to the application, network resources can b...
 
Towards Constant Bandwidth Overhead Integrity Checking of Untrusted Data
Found in: Security and Privacy, IEEE Symposium on
By Dwaine Clarke, G. Edward Suh, Blaise Gassend, Ajay Sudan, Marten van Dijk, Srinivas Devadas
Issue Date:May 2005
pp. 139-153
We present an adaptive tree-log scheme to improve the performance of checking the integrity of arbitrarily-large untrusted data, when using only a small fixed-sized trusted state. Currently, hash trees are used to check the data. In many systems that use h...
 
Fast development of hardware-based run-time monitors through architecture framework and high-level synthesis
Found in: 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)
By Mohamed Ismail,G. Edward Suh
Issue Date:September 2012
pp. 393-400
Recent work has shown that hardware-based runtime monitoring techniques can significantly enhance security and reliability of computing systems with minimal performance and energy overheads. However, the cost and time for implementing such a hardware-based...
 
High-performance parallel accelerator for flexible and efficient run-time monitoring
Found in: 2012 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)
By Daniel Y. Deng,G. Edward Suh
Issue Date:June 2012
pp. 1-12
This paper proposes Harmoni, a high performance hardware accelerator architecture that can support a broad range of run-time monitoring and bookkeeping functions. Unlike custom hardware, which offers very little configurability after it has been fabricated...
   
Efficient Timing Channel Protection for On-Chip Networks
Found in: Networks-on-Chip, International Symposium on
By Yao Wang,G. Edward Suh
Issue Date:May 2012
pp. 142-151
On-chip network is often dynamically shared among applications that are concurrently running on a chip-multiprocessor (CMP). In general, such shared resources imply that applications can affect each other's timing characteristics through interference in sh...
 
Precise exception support for decoupled run-time monitoring architectures
Found in: Computer Design, International Conference on
By Daniel Y. Deng,G. Edward Suh
Issue Date:October 2011
pp. 437-438
Recently, researchers have proposed decoupled monitoring architectures that utilize parallel hardware such as multi-cores or accelerators to enable fine-grained security and reliability checks with low overheads. However, today's decoupled monitoring archi...
 
FlexCache: Field Extensible Cache Controller Architecture Using On-chip Reconfigurable Fabric
Found in: International Conference on Field Programmable Logic and Applications
By Daniel Lo,Greg Malysa,G. Edward Suh
Issue Date:September 2011
pp. 244-251
In today's microprocessors, the cache architecture is highly optimized for one particular design and cannot be changed after fabrication. While allowing efficient implementations in dedicated logic, this inflexibility also implies that new techniques canno...
 
A non-volatile microcontroller with integrated floating-gate transistors
Found in: Dependable Systems and Networks Workshops
By Wing-kei Yu,Shantanu Rajwade,Sung-En Wang,Bob Lian,G. Edward Suh,Edwin Kan
Issue Date:June 2011
pp. 75-80
We present a non-volatile processor architecture where its entire state can be almost instantly stored and restored in a non-volatile fashion. This capability is attractive for embedded or mobile devices in highly energy constrained environments. The non-v...
 
Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Daniel Y. Deng, Daniel Lo, Greg Malysa, Skyler Schneider, G. Edward Suh
Issue Date:December 2010
pp. 137-148
This paper proposes Flex Core, a hybrid processor architecture where an on-chip reconfigurable fabric (FPGA) is tightly coupled with the main processing core. Flex Core provides an efficient platform that can support a broad range of run-time monitoring an...
 
Diastolic arrays: Throughput-driven reconfigurable computing
Found in: Computer-Aided Design, International Conference on
By Myong Hyon Cho, Chih-Chi Cheng, Michel Kinsy, G. Edward Suh, Srinivas Devadas
Issue Date:November 2008
pp. 457-464
Diastolic arrays are arrays of processing elements that communicate exclusively through First-In First-Out (FIFO) queues. FIFO virtualization units enable relaxed timing of data transfers, and include hardware support to guarantee bandwidth and buffer spac...
 
Efficient Memory Integrity Verification and Encryption for Secure Processors
Found in: Microarchitecture, IEEE/ACM International Symposium on
By G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas
Issue Date:December 2003
pp. 339
Secure processors enable new sets of applications such as commercial grid computing, software copy-protection, and secure mobile agents by providing security from both physical and software attacks. This paper proposes new hardware mechanisms for memory in...
 
Low-overhead and high coverage run-time race detection through selective meta-data management
Found in: 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
By Ruirui Huang,Erik Halberg,Andrew Ferraiuolo,G. Edward Suh
Issue Date:February 2014
pp. 96-107
This paper presents an efficient hardware architecture that enables run-time data race detection with high coverage and minimal performance overhead. Run-time race detectors often rely on the happens-before vector clock algorithm for accuracy, yet suffer f...
   
Timing channel protection for a shared memory controller
Found in: 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
By Yao Wang,Andrew Ferraiuolo,G. Edward Suh
Issue Date:February 2014
pp. 225-236
This paper proposes a new memory controller design that enables secure sharing of main memory among mutually mistrusting parties by eliminating memory timing channels. This study demonstrates that shared memory controllers are vulnerable to both side chann...
   
Non-race concurrency bug detection through order-sensitive critical sections
Found in: Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA '13)
By Erik Halberg, G. Edward Suh, Ruirui Huang
Issue Date:June 2013
pp. 655-666
This paper introduces a new heuristic condition for non-race concurrency bugs, named order-sensitive critical sections, and proposes a run-time bug detection scheme based on the condition. The order-sensitive critical sections are defined as a pair of crit...
     
Hardware enhanced security
Found in: Proceedings of the 2012 ACM conference on Computer and communications security (CCS '12)
By G. Edward Suh, Ruby Lee, Simha Sethumadhavan
Issue Date:October 2012
pp. 1052-1052
Building a secure computing system requires careful coordination among all layers in the system from hardware to software. Even if secure by itself, a higher layer protection mechanism may be bypassed if lower layer software or hardware is vulnerable. Addi...
     
SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading
Found in: Proceeding of the 38th annual international symposium on Computer architecture (ISCA '11)
By Edwin Kan, G. Edward Suh, Ruirui Huang, Sarah Q. Xu, Sung-En Wang, Wing-kei S. Yu
Issue Date:June 2011
pp. 247-258
Large register files are common in highly multi-threaded architectures such as GPUs. This paper presents a hybrid memory design that tightly integrates embedded DRAM into SRAM cells with a main application to reducing area and power consumption of multi-th...
     
IVEC: off-chip memory integrity protection for both security and reliability
Found in: Proceedings of the 37th annual international symposium on Computer architecture (ISCA '10)
By G. Edward Suh, Ruirui Huang
Issue Date:June 2010
pp. 72-ff
This paper proposes a unified off-chip memory integrity protection scheme, named IVEC. Today, a system needs two independent mechanisms in order to protect the memory integrity from both physical attacks and random errors. Integrity verification schemes de...
     
Orthrus: efficient software integrity protection on multi-cores
Found in: Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems (ASPLOS '10)
By Daniel Y. Deng, G. Edward Suh, Ruirui Huang
Issue Date:March 2010
pp. 222-230
This paper proposes an efficient hardware/software system that significantly enhances software security through diversified replication on multi-cores. Recent studies show that a large class of software attacks can be detected by running multiple versions ...
     
Implementing dynamic information flow tracking on microprocessors with integrated FPGA fabric (abstract only)
Found in: Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays (FPGA '10)
By Daniel Lo, Daniel Y. Deng, G. Edward Suh, Greg Malysa, Skyler Schneider
Issue Date:February 2010
pp. 285-285
Today, incorporating a new hardware feature into a modern microprocessor is a highly time consuming and expensive process due to long design cycles and high costs of design and verification. To address this challenge, this paper proposes a hybrid processor...
     
Hardware authentication leveraging performance limits in detailed simulations and emulations
Found in: Proceedings of the 46th Annual Design Automation Conference (DAC '09)
By Andrew H. Chan, Daniel Y. Deng, G. Edward Suh
Issue Date:July 2009
pp. 682-687
This paper proposes a novel approach to check the authenticity of hardware based on the inevitable performance gap between real hardware and simulations or emulations that impersonate it. More specifically, we demonstrate that each processor design can be ...
     
Physical unclonable functions for device authentication and secret key generation
Found in: Proceedings of the 44th annual conference on Design automation (DAC '07)
By G. Edward Suh, Srinivas Devadas
Issue Date:June 2007
pp. 9-14
Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that exploit inherent delay characteristics of wires and transistors that differ ...
     
Secure program execution via dynamic information flow tracking
Found in: Proceedings of the 11th international conference on Architectural support for programming languages and operating systems (ASPLOS-XI)
By David Zhang, G. Edward Suh, Jae W. Lee, Srinivas Devadas
Issue Date:October 2004
pp. 97-105
We present a simple architectural mechanism called dynamic information flow tracking that can significantly improve the security of computing systems with negligible performance overhead. Dynamic information flow tracking protects programs against maliciou...
     
AEGIS: architecture for tamper-evident and tamper-resistant processing
Found in: Proceedings of the 17th annual international conference on Supercomputing (ICS '03)
By Blaise Gassend, Dwaine Clarke, G. Edward Suh, Marten van Dijk, Srinivas Devadas
Issue Date:June 2003
pp. 160-171
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture assumes that all components external to the processor, such as memory, are untru...
     
Embedded intelligent SRAM
Found in: Proceedings of the 40th conference on Design automation (DAC '03)
By G. Edward Suh, Prabhat Jain, Srinivas Devadas
Issue Date:June 2003
pp. 869-874
Many embedded systems use a simple pipelined RISC processor for computation and an on-chip SRAM for data storage. We present an enhancement called Intelligent SRAM (ISRAM) that consists of a small computation unit with an accumulator that is placed near th...
     
Analytical cache models with applications to cache partitioning
Found in: Proceedings of the 15th international conference on Supercomputing (ICS '01)
By G. Edward Suh, Larry Rudolph, Srinivas Devadas
Issue Date:June 2001
pp. 1-12
An accurate, tractable, analytic cache model for time-shared systems is presented, which estimates the overall cache miss-rate of a multiprocessing system with any cache size and time quanta. The input to the model consists of the isolated miss-rate curves...
     
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