Search For:

Displaying 1-40 out of 40 total
RT-Level ITC'99 Benchmarks and First ATPG Results
Found in: IEEE Design and Test of Computers
By Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
Issue Date:July 2000
pp. 44-53
<p>New design flows require reducing work at the gate level and perfoming most activities before the synthesis step, including evaluatation of testability of circuits. We propose a suite of RT-level benchmarks that help improve research in high-level...
 
Circular Self-Test Path for FSMs
Found in: IEEE Design and Test of Computers
By Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
Issue Date:December 1996
pp. 50-60
<p>The Circular Self-Test Path (CSTP) technique is an attractive method for automatically transforming sequential circuits generated by automatic synthesis tools into BIST structures. The first goal of this article is to assess the effectiveness of t...
 
Formal Verification of Device State Chart Models
Found in: Intelligent Environments, International Conference on
By Fulvio Corno,Muhammad Sanaullah
Issue Date:July 2011
pp. 66-73
Design and development of increasingly complex intelligent environments require rich design flows that include strong validation and verification methodologies. Formal verification techniques are often advocated, and they require formally described models ...
 
FaSet: A Set Theory Model for Faceted Search
Found in: Web Intelligence and Intelligent Agent Technology, IEEE/WIC/ACM International Conference on
By Dario Bonino, Fulvio Corno, Laura Farinetti
Issue Date:September 2009
pp. 474-481
Faceted classification is a technique originated and refined in the library science field, that recently gained a lot of attention for creating efficient search interfaces for web databases. Faceted search requires the definition of a formal representation...
 
Self-Similarity Metric for Index Pruning in Conceptual Vector Space Models
Found in: Database and Expert Systems Applications, International Workshop on
By Dario Bonino, Fulvio Corno
Issue Date:September 2008
pp. 225-229
One of the critical issues in search engines is the size of search indexes: as the number of documents handled by an engine increases, the search must preserve its efficiency, despite the growth of indexing structures. A widely agreed solution to this prob...
 
Versatile RDF Representation for Multimedia Semantic Search
Found in: Tools with Artificial Intelligence, IEEE International Conference on
By Dario Bonino, Fulvio Corno, Paolo Pellegrino
Issue Date:October 2007
pp. 32-38
trieval technologies into mainstream web applications depends on the ease of adoption and re-use of existing information and meta-data. While for textual information, analysis of the text content is quite standardized, for multimedia resources many archive...
 
Composing Web Services on the Basis of Natural Language Requests
Found in: Web Services, IEEE International Conference on
By Alessio Bosca, Andrea Ferrato, Fulvio Corno, Ilenia Congiu, Giuseppe Valetto
Issue Date:July 2005
pp. 817-818
The introduction of the Semantic Web paradigm in Service-oriented Architectures enables explicit representation and reasoning about services, via a semantically rich description of their operations. We propose an approach towards service selection and comp...
   
An Agent Based Autonomic Semantic Platform
Found in: Autonomic Computing, International Conference on
By Dario Bonino, Alessio Bosca, Fulvio Corno
Issue Date:May 2004
pp. 189-196
<p>In 2001, two distinct revolutionary approaches to distributed system integration and web content diffusion were proposed: Autonomic Computing and the Semantic Web. These approaches are currently two of the most active research fields in the inform...
 
Automatic Test Program Generation: A Case Study
Found in: IEEE Design and Test of Computers
By Fulvio Corno, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero
Issue Date:March 2004
pp. 102-109
Comprehensive coverage measurement should guide an effective testbench generation approach. Today, feedback from coverage to test generation often requires manual work; it is desirable to implement a framework that automates this feedback process. The auth...
 
DOSE: A Distributed Open Semantic Elaboration Platform
Found in: Tools with Artificial Intelligence, IEEE International Conference on
By Dario Bonino, Fulvio Corno, Laura Farinetti
Issue Date:November 2003
pp. 580
The paper proposes a Distributed Open Semantic Elaboration platform based on a modular multilingual enabled architecture, which includes ontology, annotations, lexical entities and search functions. The platform is implemented as a distributed set of servi...
 
A Real-Time Evolutionary Algorithm for Web Prediction
Found in: Web Intelligence, IEEE / WIC / ACM International Conference on
By Dario Bonino, Fulvio Corno, Giovanni Squillero
Issue Date:October 2003
pp. 139
As an increasing number of users access information on the World Wide Web, there is a opportunity to improve well known strategies for web caching, prefetching, dynamic user modeling and dynamic site customization in order to obtain better subjective perfo...
 
Evolutionary Test Program Induction for Microprocessor Design Verification
Found in: Asian Test Symposium
By Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero
Issue Date:November 2002
pp. 368
Design verification is a crucial step in the design of any electronic device. Particularly when microprocessor cores are considered, devising appropriate test cases may be a difficult task. This paper presents a methodology able to automatically induce a t...
 
Analysis of the Equivalences and Dominances of Transient Faults at the RT Level
Found in: On-Line Testing Workshop, IEEE International
By Luis Berrojo, Isabel González, Luis Entrena, Celia López, Fulvio Corno, Matteo Sonza, Giovanni Squillero
Issue Date:July 2002
pp. 193
This work presents a study for tackling transient faults at the RT-level and outlines the techniques devised and implemented to speed-up fault-injection campaigns, detecting the equivalences and dominancies between faults in order to collapse them. Experim...
   
An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation
Found in: VLSI Test Symposium, IEEE
By Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza-Reorda, Giovanni Squillero, Luis Entrena, Celia Lopez
Issue Date:May 2002
pp. 0229
When designing a VL I circuits, most of the efforts are now performed at levels of abstractions higher than gate. Correspondingly to this clear trend, there is a growing request to tackle safety-critical issues directly at the RT-level. This paper presents...
 
Effective Techniques for High-Level ATPG
Found in: Asian Test Symposium
By Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero
Issue Date:November 2001
pp. 225
The ASIC design flow is rapidly moving towards higher description levels, and most design activities are now performed at the RT-level. However, test-related activities are lacking behind this trend, mainly since effective fault models and test pattern gen...
 
Exploiting the Selfish Gene Algorithm for Evolving Cellular Automata
Found in: Neural Networks, IEEE - INNS - ENNS International Joint Conference on
By Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
Issue Date:July 2000
pp. 6577
This paper shows an application in the field of Electronic CAD of the Selfish Gene algorithm, an evolutionary algorithm based on a recent interpretation of the Darwinian theory. Testing is a key issue in the design and production of digital circuits and th...
 
High-Level Observability for Effective High-Level ATPG
Found in: VLSI Test Symposium, IEEE
By Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
Issue Date:May 2000
pp. 411
This paper focuses on observability, one of the open issues in High-Level test generation. Three different approximate metrics for considering observability during RT-level ATPG are presented. Metrics range from a really naive and optimistic one too more s...
 
Low Power BIST via Non-Linear Hybrid Cellular Automata
Found in: VLSI Test Symposium, IEEE
By Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante
Issue Date:May 2000
pp. 29
In the last decade, researchers devoted many efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption during test operation mode was usually neglected. However, during test application circuits a...
 
Optimal Vector Selection for Low Power BIST
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaudengo, Massimo Violante
Issue Date:November 1999
pp. 219
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption during test operation mode was usually neglected. However, during test application...
 
RT-level TPG Exploiting High-Level Synthesis Information
Found in: VLSI Test Symposium, IEEE
By Silvia Chiusano, Fulvio Corno, Paolo Prinetto
Issue Date:April 1999
pp. 341
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test pattern generation for circuits described at the RT-level. The approach is based o...
 
Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Enrique San Millán, Luis Entrena, José A. Espejo, Silvia Chiusano, Fulvio Corno
Issue Date:March 1999
pp. 516
This paper presents a new integrated approach to logic optimization for sequential circuits. The approach is based on the Redundancy Addition and Removal algorithm, which is based on Automatic Test Pattern Generation (ATPG) techniques, and improves it usin...
 
A Test Pattern Generation Algorithm Exploiting Behavioral Information
Found in: Asian Test Symposium
By Silvia Chiusano, Fulvio Corno, Paolo Prinetto
Issue Date:December 1998
pp. 480
This paper aims at broadening the scope of hierarchical ATPG to the behavioral-level The main problem of using behavioral information for ATPG is the mismatch of timing models between the behavioral- and gate-levels. Theoretical analysis shows that the def...
 
Enhancing Topological ATPG with High-Level Information and Symbolic Techniques
Found in: Computer Design, International Conference on
By Fulvio Corno, Matteo Sonza Reorda, Roberto Vietti, Janak H. Patel, Elizabeth M. Rudnick
Issue Date:October 1998
pp. 504
This paper proposes a method to enhance topological ATPG algorithms by exploiting some information computed through symbolic techniques. Since symbolic techniques can only be applied to small circuits, suitable circuit portions (named macros) are first sel...
 
VEGA: A Verification Tool Based on Genetic Algorithms
Found in: Computer Design, International Conference on
By Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
Issue Date:October 1998
pp. 321
While modern state-of-the-art optimization techniques can handle designs with up to hundreds of flip-flops, equivalence verification is still a challenging task in many industrial design flows. This paper presents a new verification methodology that, while...
 
Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
Issue Date:February 1998
pp. 570
A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate level. Several sequences are derived to ensure 100% coverage of all statements ...
 
Integrating Online and Offline Testing of a Switching Memory
Found in: IEEE Design and Test of Computers
By Stefano Barbagallo, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
Issue Date:January 1998
pp. 63-70
The article describes the architecture of a circuit used in a telephone switching unit and focuses on its on-line and off-line test features. Several techniques have been exploited: BIST is adopted to test some embedded memories, Partial Scan allows the te...
 
Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs
Found in: Test Conference, International
By Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
Issue Date:October 1996
pp. 558
The partial scan approach is now widely adopted and several commercial tools support this technique. However, there is no general agreement on how to select the Scan Flip Flops: in general each technique is tailored to a particular ATPG algorithm and resul...
 
Self-Checking and Fault Tolerant Approaches Can Help BIST Fault Coverage: A Case Study
Found in: European Design and Test Conference
By Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
Issue Date:March 1996
pp. 610
This paper describes the design of a FIFO component with BIST capabilities. The component is now being used in the Italtel standard library and is exploited in several industrial designs. Our main contribution is to show how the effectiveness of complex BI...
   
JEERP: Energy-Aware Enterprise Resource Planning
Found in: IT Professional
By Dario Bonino,Luigi De Russis,Fulvio Corno,Gianni Ferrero
Issue Date:July 2014
pp. 50-56
Ever-increasing energy costs and saving requirements, especially in enterprise contexts, are pushing the limits of enterprise resource planning (ERP) to better account for energy, with component-level asset granularity. The authors use an application-orien...
 
Innovative and Disruptive Technologies [From the Editors]
Found in: IT Professional
By Phillip A. Laplante,Tom Jepsen,Joseph Williams,Fulvio Corno
Issue Date:May 2013
pp. 4-5
Without disruptive technologies, human progress would likely be slower and not marked by quantum leaps due to certain advancements. This special issue focuses on computing technologies that show promise of being the next cycle of innovation and disruption.
 
Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
Issue Date:March 1999
pp. 754
While modern state-of-the-art optimization techniques can handle designs with hundreds of flip-flops, the verification of the correctness of the design is still a challenging task in many in-dustrial design flows. This paper presents a new verification met...
 
Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante
Issue Date:February 1998
pp. 670
Partial Scan techniques have been widely accepted as an effective solution to improve sequential ATPG performance while keeping acceptable area and performance overheads. Several techniques for flip-flop selection based on structural analysis have been pre...
 
Testability analysis and ATPG on behavioral RT-level VHDL
Found in: Test Conference, International
By Fulvio CORNO, Paolo PRINETTO, Matteo SONZA REORDA
Issue Date:November 1997
pp. 753
This paper proposes an environment to address Testability Analysis and Test Pattern Generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fault model and an ATPG algorithm, is experimentally shown to provide a good est...
 
The smart home controller on your wrist
Found in: Proceedings of the 2013 ACM conference on Pervasive and ubiquitous computing adjunct publication (UbiComp '13 Adjunct)
By Dario Bonino, Fulvio Corno, Luigi De Russis
Issue Date:September 2013
pp. 785-792
This paper addresses human-home interaction mediated by everyday objects, with a particular focus on wrist watches. Everyday wrist-worn devices are turned into flexible home access points by exploiting a modular architecture independent from the underlying...
     
Integrated speech and gaze control for realistic desktop environments
Found in: Proceedings of the 2008 symposium on Eye tracking research & applications (ETRA '08)
By Emiliano Castellina, Fulvio Corno, Paolo Pellegrino
Issue Date:March 2008
pp. 19-23
Nowadays various are the situations in which people need to interact with a Personal Computer without having the possibility to use traditional pointing devices, such as a keyboard or a mouse. In the latest years, various alternatives to the classical inpu...
     
A reusable 3D visualization component for the semantic web
Found in: Proceedings of the twelfth international conference on 3D web technology (Web3D '07)
By Alessio Bosca, Dario Bonino, Fulvio Corno, Marco Comerio, Simone Grega
Issue Date:April 2007
pp. 89-96
Ontology visualization and exploration is not a trivial task as many issues can affect the effectiveness of interactions. As ontologies are, in the general case, quite connected graphs where concepts are the nodes and semantic relationships the edges, the ...
     
Domotic house gateway
Found in: Proceedings of the 2006 ACM symposium on Applied computing (SAC '06)
By Dario Bonino, Fulvio Corno, Paolo Pellegrino
Issue Date:April 2006
pp. 1915-1920
This paper presents a domotic house gateway capable of seamlessly interacting with different devices from heterogeneous domotic systems and appliances. Such a gateway also provides the possibility to automate device cooperation through an embedded rule-bas...
     
Automatic learning of text-to-concept mappings exploiting WordNet-like lexical networks
Found in: Proceedings of the 2005 ACM symposium on Applied computing (SAC '05)
By Dario Bonino, Federico Pescarmona, Fulvio Corno
Issue Date:March 2005
pp. 1639-1644
A great jump towards the advent of the Semantic Web will take place when a critical mass of web resources is available for use in a semantic way. This goal can be reached by the creation of semantic meta-data in the publication workflow, or by the developm...
     
The selfish gene algorithm: a new evolutionary optimization strategy
Found in: Proceedings of the 1998 ACM symposium on Applied Computing (SAC '98)
By Fulvio Corno, Giovanni Squillero, Matteo Sonza Reorda
Issue Date:February 1998
pp. 349-355
This paper describes the effects of program restructuring in a dataflow environment. Previous studies showed that dataflow programs can exhibit locality and that a memory hierarchy is feasible in a dataflow environment. This study shows that the order in w...
     
SAARA: a simulated annealing algorithm for test pattern generation for digital circuits
Found in: Proceedings of the 1997 ACM symposium on Applied computing (SAC '97)
By Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaudenpgo, Paolo prinetto
Issue Date:April 1997
pp. 228-232
This paper describes the effects of program restructuring in a dataflow environment. Previous studies showed that dataflow programs can exhibit locality and that a memory hierarchy is feasible in a dataflow environment. This study shows that the order in w...
     
 1