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Displaying 1-8 out of 8 total
Cross-Correlation Cartography
Found in: Reconfigurable Computing and FPGAs, International Conference on
By Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
Issue Date:December 2010
pp. 268-273
Side channel and fault injection attacks are a major threat to cryptographic applications of embedded systems. Best performances for these attacks are achieved by focusing sensors or injectors on the sensible parts of the application, by means of dedicated...
 
Evaluation of White-Box and Grey-Box Noekeon Implementations in FPGA
Found in: Reconfigurable Computing and FPGAs, International Conference on
By Zouha Cherif, Florent Flament, Jean-Luc Danger, Shivam Bhasin, Sylvain Guilley, Hervé Chabanne
Issue Date:December 2010
pp. 310-315
White-box implementations of cryptographic algorithms aim to denying the key readout even if the source code embedding the key is disclosed. They are based on sets of large tables perfectly known by the user but including unknown encoding functions. While ...
 
Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics
Found in: IEEE Transactions on Computers
By Sylvain Guilley, Laurent Sauvage, Florent Flament, Vinh-Nga Vong, Philippe Hoogvorst, Renaud Pacalet
Issue Date:September 2010
pp. 1250-1263
Cryptographic circuits are nowadays subject to attacks that no longer focus on the algorithm but rather on its physical implementation. Attacks exploiting information leaked by the hardware implementation are called side-channel attacks (SCAs). Among these...
 
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow
Found in: Reconfigurable Computing and FPGAs, International Conference on
By Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane
Issue Date:December 2009
pp. 213-218
The main challenge when implementing cryptographic algorithms in hardware is to protect them against attacks that target directly the device. Two strategies are customarily employed by malevolent adversaries: observation and differential perturbation attac...
 
DPL on Stratix II FPGA: What to Expect?
Found in: Reconfigurable Computing and FPGAs, International Conference on
By Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
Issue Date:December 2009
pp. 243-248
FPGA design of side channel analysis countermeasure using unmasked dual-rail with precharge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful differential placement and routing, whereas both FPGA layout and ...
 
Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors
Found in: IEEE Design and Test of Computers
By Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu
Issue Date:November 2007
pp. 546-555
This article presents a comprehensive back-end design flow that enables the realization of constant-power cryptoprocessors, natively protected against side-channel attacks exploiting the instant power consumption. The proposed methodology is based on a ful...
 
Countering early evaluation: an approach towards robust dual-rail precharge logic
Found in: Proceedings of the 5th Workshop on Embedded Systems Security (WESS '10)
By Florent Flament, Jean-Luc Danger, Nidhal Selmane, Shivam Bhasin, Sylvain Guilley
Issue Date:October 2010
pp. 1-8
Wave Dynamic Differential Logic (WDDL) is a hiding countermeasure to thrawt side channel attacks (SCA). It suffers from a vulnerability called Early Evaluation, i.e. calculating output before all inputs are valid. This causes delay biases in WDDL even when...
     
An 8x8 run-time reconfigurable FPGA embedded in a SoC
Found in: Proceedings of the 45th annual conference on Design automation (DAC '08)
By Florent Flament, Jean-Luc Danger, Philippe Hoogvorst, Sumanta Chaudhuri, Sylvain Guilley
Issue Date:June 2008
pp. 1-30
This paper presents a RTR FPGA embedded in a System on Chip fabricated in 130nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. We explain the measures taken in the FPGA design to guarantee RTR functionali...
     
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