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Displaying 1-10 out of 10 total
Hardware Reuse in Modern Application-Specific Processors and Accelerators
Found in: Digital Systems Design, Euromicro Symposium on
By Alexandre S. Nery,Lech Jozwiak,Menno Lindwer,Mauro Cocco,Nadia Nedjah,Felipe M.G. França
Issue Date:September 2011
pp. 140-147
Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)configurable application specific instruc...
 
SpMT WaveCache: Exploiting Thread-Level Parallelism in WaveScalar
Found in: Computer Science and Information Engineering, World Congress on
By Songwen Pei, Baifeng Wu, Min Du, Gang Chen, Leandro A.J. Marzulo, Felipe M.G. Franca
Issue Date:April 2009
pp. 530-535
Speculative Multithreading (SpMT) increases the performance by means of executing multiple threads speculatively to exploit thread-level parallelism. By combining software and hardware approaches, we have improved the capabilities of previous WaveScalar IS...
 
Scheduling Cyclic Task Graphs with SCC-Map
Found in: 2012 3rd Workshop on Applications for Multi-Core Architectures (WAMCA)
By Alexandre Sardinha,Tiago A.O. Alves,Leandro A.J. Marzulo,Felipe M.G. Franca,Valmir C. Barbosa,Vitor Santos Costa
Issue Date:October 2012
pp. 54-59
The Dataflow execution model has been shown to be a good way of exploiting TLP, making parallel programming easier. In this model, tasks must be mapped to processing elements (PEs) considering the trade-off between communication and parallelism. Previous w...
 
TALM: A Hybrid Execution Model with Distributed Speculation Support
Found in: Computer Architecture and High Performance Computing Workshops, International Symposium on
By Leandro A.J. Marzulo, Tiago A.O. Alves, Felipe M.G. França, Vítor Santos Costa
Issue Date:October 2010
pp. 31-36
Parallel programming has become mandatory to fully exploit the potential of modern CPUs. The data-flow model provides a natural way to exploit parallelism. However, traditional data-flow programming is not trivial: specifying dependencies and control using...
 
Transactional WaveCache: Towards Speculative and Out-of-Order DataFlow Execution of Memory Operations
Found in: Computer Architecture and High Performance Computing, Symposium on
By Leandro A.J. Marzulo, Felipe M.G. Franca, Vítor Santos Costa
Issue Date:November 2008
pp. 183-190
The WaveScalar is the first DataFlow Architecture that can efficiently provide the sequential memory semantics required by imperative languages. This work presents a speculative memory disambiguation mechanism for this architecture, the Transaction WaveCac...
 
Pyndorama, Integrating Web Learning System in a Single Application
Found in: Internet and Web Applications and Services, International Conference on
By Carlo E.T. de Oliveira, Livia M. Castro, Luiz G.L. Moura, Felipe M.G. Franca
Issue Date:May 2007
pp. 51
Notwithstanding all the technology being invested in education, students still have to cope with a massive input of instructional information. However, many insulated initiatives from education community have been put forward. Each initiative by itself may...
 
A Software Architecture for the Provisioning of Mobile Services in Peer-to-Peer Environments
Found in: Internet and Web Applications and Services, International Conference on
By Fabricio B. Goncalves, Carlo E.T. Oliveira, Izalmo Silva, Luiz G.L. Moura, Felipe M.G. Franca
Issue Date:May 2007
pp. 9
Service-Oriented Computing (SOC) is the computational paradigm that utilizes services as fundamental elements to develop applications/solutions. To build a service model, SOC relies on the Service-Oriented Architecture (SOA), which is a way of reorganizing...
 
An FPGA-Based Fan Beam Image Reconstruction Module
Found in: Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
By Luiz Maltar, Felipe M.G. França, Vladimir C. Alves, Cláudio L. Amorim
Issue Date:April 1999
pp. 312
This work is concerned with the FPGA implementation of pipelined SRT division, a clear bottleneck in the process of tomographic image reconstruction using Filtered Back-Projection (FBP) from fan beam projections. Our solution adopts radix-4 form in the quo...
 
Implementation of RNS Addition and RNS Multiplication into FPGAs
Found in: Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
By Luiz Maltar, Felipe M.G. França, Vladimir C. Alves, Cláudio L. Amorim
Issue Date:April 1998
pp. 331
Abstract- We investigate whether arithmetic operations based on Residue Number systems (RNS) are cost-effective solutions to implement DSP applications into reconfigurable hardware. We simulated several RNS addition and multiplication implementations by va...
 
Building Artificial CPGs with Asymmetric Hopfield Networks
Found in: Neural Networks, IEEE - INNS - ENNS International Joint Conference on
By Felipe M.G. França, Zhijun Yang
Issue Date:July 2000
pp. 4290
This paper presents a novel approach to the emulation of locomotor central pattern generators (CPGs) of legged animals. Based on Scheduling by Multiple Edge Reversal (SMER), a simple but powerful distributed algorithm, it is shown how oscillatory building ...
 
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