Search For:

Displaying 1-21 out of 21 total
A Time-Multiplexed Reconfigurable Neuroprocessor
Found in: IEEE Micro
By Fadi N. Sibai, Sunil D. Kulkarni
Issue Date:January 1997
pp. 58-65
We present the architecture and VLSI circuit design of a multilayered pulse-stream neuroprocessor. This neuroprocessor design uses a mixed analog/digital implementation to obtain an efficient use of chip area and operating speed. The processing element (PE...
 
Low Diameter Unicast On-Chip Interconnection Networks for Many-Core Embedded Systems
Found in: Complex, Intelligent and Software Intensive Systems, International Conference
By Fadi N. Sibai
Issue Date:February 2010
pp. 944-949
It is critical for the network-on-chip in embedded multi-core and many-core chips to be scalable while limiting power consumption. With the router power dominating the network’s power, one way to achieve this goal is by the design of on-chip interconnectio...
 
Parallel Orthomin Equation Solver on the Cell Broadband Engine
Found in: Parallel Computing in Electrical Engineering, International Conference on
By Fadi N. Sibai, Hashir Karim Kidwai
Issue Date:April 2011
pp. 105-110
This paper presents our parallelization and implementation of the ORTHOMIN solver on the Cell Broadband Engine. The solution of linear systems of equation sis one of the most central processing unit-intensive steps in many engineering and simulation applic...
 
Which On-Chip Interconnection Network for 16-core MPSoCs?
Found in: Complex, Intelligent and Software Intensive Systems, International Conference
By Fadi N. Sibai
Issue Date:February 2010
pp. 625-630
On-chip interconnection networks (OCINs) in many-core systems are key to the system’s performance scalability. OCIN design constraints are governed by power, cost, latency, ease of routing, as well as others. As chips with 16 cores are around the corner, w...
 
Gauging the OpenSourceMark Benchmark in Measuring CPU Performance
Found in: Computer and Information Science, ACIS International Conference on
By Fadi N. Sibai
Issue Date:May 2008
pp. 433-438
We analyze COSBI’s Open Source Mark (OSMark) benchmark [1] in measuring CPU performance in desktop personal computers. We select and focus on selected tests of the benchmark targeting the CPU which we also profile. We run the benchmark on two personal comp...
 
A Fault-Tolerant Digital Artificial Neuron
Found in: IEEE Design and Test of Computers
By Fadi N. Sibai
Issue Date:October 1993
pp. 76-82
<p>A simple fault-tolerant digital artificial neuron is introduced. Two digital implementations based on two different adders are examined. Reliability, fault coverage, and hardware redundancy analyses are carried out to characterize the proposed fau...
 
V-Set Cache Design for LLC of Multi-core Processors
Found in: 2012 IEEE 14th Int'l Conf. on High Performance Computing and Communication (HPCC) & 2012 IEEE 9th Int'l Conf. on Embedded Software and Systems (ICESS)
By Ali A. El-Moursy,Fadi N. Sibai
Issue Date:June 2012
pp. 995-1000
With the increase in the number of the cores integrated in the single-chip microprocessor, the design of an efficient shared Last-Level-Cache (LLC) becomes more critical to the microprocessor performance. In this paper the author proposes v-set cache desig...
 
A Two-Dimensional Low-Diameter Scalable On-Chip Network for Interconnecting Thousands of Cores
Found in: IEEE Transactions on Parallel and Distributed Systems
By Fadi N. Sibai
Issue Date:February 2012
pp. 193-201
This paper introduces the Spidergon-Donut (SD) on-chip interconnection network for interconnecting 1,000 cores in future MPSoCs and CMPs. Unlike the Spidergon network, the SD network which extends the Spidergon network into the second dimension, significan...
 
Adapting the Hyper-Ring Interconnect for Many-Core Processors
Found in: Parallel and Distributed Processing with Applications, International Symposium on
By Fadi N. Sibai
Issue Date:December 2008
pp. 649-654
This paper makes the case for the Hyper-Ring as the interconnect or NoC for many-cores. While other prominent candidates for many-core interconnect such as the torus and mesh have superior bisection bandwidth to the HR, their cost, number of links and chip...
 
Simulation and Performance Analysis of Multi-core Thread Scheduling and Migration Algorithms
Found in: Complex, Intelligent and Software Intensive Systems, International Conference
By Fadi N. Sibai
Issue Date:February 2010
pp. 895-900
One major issue in the design of multi-core systems is scheduling execution threads on the many cores. Heterogeneity complicates the issue given the different types of cores with various functionality and power requirements. In a large multi-core chip with...
 
Parallelization and Performance Analysis of an IMPES-based Oil-Water Reservoir Simulator
Found in: High Performance Computing and Communications, 10th IEEE International Conference on
By Fadi N. Sibai, Hashir Karim Kidwai
Issue Date:June 2009
pp. 488-493
Oil reservoir simulation helps in extracting oil and in optimal well placement. This paper presents the parallelization, development, performance analysis, and profiling of a 2-phase oil-water reservoir simulator on a heterogeneous multi-core STI Cell comp...
 
Impact of L1 entire locking and L2 way locking on the performance, power consumption, and predictability of multicore real-time systems
Found in: Computer Systems and Applications, ACS/IEEE International Conference on
By Abu Asaduzzaman, Imad Mahgoub, Fadi N. Sibai
Issue Date:May 2009
pp. 705-711
Based on the recent design trend from giant chip-vendors, multicore systems are being deployed with multilevel caches to achieve higher levels of performance. Supporting real-time applications on multicore systems becomes a great challenge as caches are po...
 
Highly parallel image processing on the STI Cell
Found in: Computer Systems and Applications, ACS/IEEE International Conference on
By Hashir Karim Kidwai, Fadi N. Sibai, Tamer Rabie
Issue Date:May 2009
pp. 849-852
Massively deployed inside Sony PS3 platforms, the STI Cell Broadband Engine is a multi-core processor with a PowerPC host processor (PPE) and 8 synergic processor engines (SPEs). In this paper, we describe three image processing applications which we imple...
 
Parallel Video Surveillance on the Multi-core Cell Broadband Engine
Found in: Computational Sciences and Optimization, International Joint Conference on
By Tamer Rabie, Hashir Karim Kidwai, Fadi N. Sibai
Issue Date:April 2009
pp. 85-89
The IBM Cell Broadband Engine (BE) is a multi-core processor with a PowerPC host processor (PPE) and 8 synergic processor engines (SPEs). The Cell BE architecture is designed to improve upon conventional processors in terms of memory latency, bandwidth and...
 
3D Graphics Performance Scaling and Workload Decomposition and Analysis
Found in: Computer and Information Science, ACIS International Conference on
By Fadi N. Sibai
Issue Date:July 2007
pp. 604-609
With stunning visual effects, 3DMark? emerged as the leading PC benchmark for 3D gaming performance. Its tests are at the cutting edge of consumer graphics and push the limit of 3D rendering with spectacular scenes, and state of the art lighting techniques...
 
Teaching page replacement algorithms with a Java-based VM simulator
Found in: Proceedings of the 14th Western Canadian Conference on Computing Education (WCCCE '09)
By David A. Lill, Fadi N. Sibai, Maria Ma
Issue Date:May 2009
pp. 1-36
Computer system courses have long benefited from simulators in conveying important concepts to students. We have modified the Java source code of the MOSS virtual memory simulator to allow users to easily switch between different page replacement algorithm...
     
The hyper-ring network: a cost-efficient topology for scalable multicomputers
Found in: Proceedings of the 1998 ACM symposium on Applied Computing (SAC '98)
By Fadi N. Sibai
Issue Date:February 1998
pp. 607-612
This paper describes the effects of program restructuring in a dataflow environment. Previous studies showed that dataflow programs can exhibit locality and that a memory hierarchy is feasible in a dataflow environment. This study shows that the order in w...
     
Performance of the hyper-ring multicomputer
Found in: Proceedings of the 1998 ACM symposium on Applied Computing (SAC '98)
By Fadi N. Sibai
Issue Date:February 1998
pp. 598-606
This paper describes the effects of program restructuring in a dataflow environment. Previous studies showed that dataflow programs can exhibit locality and that a memory hierarchy is feasible in a dataflow environment. This study shows that the order in w...
     
Distributed routing in the recursive diamond network
Found in: Proceedings of the 1997 ACM symposium on Applied computing (SAC '97)
By Fadi N. Sibai
Issue Date:April 1997
pp. 389-392
This paper describes the effects of program restructuring in a dataflow environment. Previous studies showed that dataflow programs can exhibit locality and that a memory hierarchy is feasible in a dataflow environment. This study shows that the order in w...
     
On the impact of pipelined communication in hierarchical ring multicomputers
Found in: Proceedings of the 1997 ACM symposium on Applied computing (SAC '97)
By Fadi N. Sibai
Issue Date:April 1997
pp. 384-388
This paper describes the effects of program restructuring in a dataflow environment. Previous studies showed that dataflow programs can exhibit locality and that a memory hierarchy is feasible in a dataflow environment. This study shows that the order in w...
     
Multi-node communication in hyper-ring networks
Found in: Proceedings of the 1997 ACM symposium on Applied computing (SAC '97)
By Fadi N. Sibai
Issue Date:April 1997
pp. 380-383
This paper describes the effects of program restructuring in a dataflow environment. Previous studies showed that dataflow programs can exhibit locality and that a memory hierarchy is feasible in a dataflow environment. This study shows that the order in w...
     
 1