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Displaying 1-6 out of 6 total
An effective fast and small-area parallel-pipeline architecture for OTM-convolutional encoders
Found in: On-Line Testing Symposium, IEEE International
By Houssein Jaber, Fabrice Monteiro, Abbas Dandache
Issue Date:June 2009
pp. 257-261
With the ever increasing data throughputs required by communication application, there is an actual need for new effective architectures (small area and high speed) for circuit parts dedicated to error detecting/correcting coding (EDC/ECC). In this paper, ...
 
A fault tolerant journalized stack processor architecture
Found in: On-Line Testing Symposium, IEEE International
By Abbas Ramazani, Mohsin Amin, Fabrice Monteiro, Camille Diou, Abbas Dandache
Issue Date:June 2009
pp. 201-202
Dependable architectures play an important role in many areas that impact our lives. Dependability is achieved by using a set of analysis and design techniques that increases the complexity and consequently the cost of systems. In this paper, to meet low c...
 
Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes
Found in: On-Line Testing Symposium, IEEE International
By Fabrice Monteiro, Stanislaw J. Piestrak, Houssein Jaber, Abbas Dandache
Issue Date:July 2007
pp. 199-200
The problem of designing a fault-secure interface between a fault-tolerant RAM memory system and a transmission channel, both protected against errors using cyclic linear error detecting and/or correcting codes is considered. The main idea relies on using ...
   
Modeling of Transients Caused by a Laser Attack on Smart Cards
Found in: On-Line Testing Symposium, IEEE International
By Damien Leroy, Stanisław J. Piestrak, Fabrice Monteiro, Abbas Dandache
Issue Date:July 2005
pp. 193-194
Several techniques for extracting data from smart cards have been described in the literature, including the so called differential fault analysis (DFA) that relies on perturbing the chip operations to deduce the data. In this paper, we present some experi...
   
Fast Configurable Polynomial Division for Error Control Coding Applications
Found in: On-Line Testing Workshop, IEEE International
By Fabrice Monteiro, Abbas Dandache, Bernard Lepley
Issue Date:July 2001
pp. 0158
Abstract: The motivation for this paper is the need for high levels of reability in modern telecommunication systems requiring very high data transmission rates. The search for technologicaly independent solutions, easy to implement on low cost and popular...
 
Design of Fault-Secure Encoders for a Class of Systematic Error Correcting Codes
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Stanislaw J. Piestrak, Abbas Dandache, Fabrice Monteiro
Issue Date:October 2001
pp. 0314
In this paper, we consider the open problem of designing fault-secure encorders for various systematic error correcting codes (ECCs). The main idea relies on generating in parallel both the error correcting and detecting check bits which are regenerated fr...
 
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