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SET Fault Tolerant Combinational Circuits Based on Majority Logic
Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Á. Michels, L. Petroli, C.A.L. Lisbôa, F. Kastensmidt, L. Carro
Issue Date:October 2006
This work proposes the use of analog majority gates to implement combinational circuits that are intrinsically tolerant to transient faults. We propose a new type of voter circuit that uses some knowledge from the analog design arena, and show that these c...
Comparing transient-fault effects on synchronous and on asynchronous circuits
On-Line Testing Symposium, IEEE International
By R. Possamai Bastos, Y. Monnet, G. Sicard, F. Kastensmidt, M. Renaudin, R. Reis
Issue Date:June 2009
A methodology to evaluate transient-fault effects on synchronous and asynchronous is presented in this work. It is developed by means of fault-injection simulation campaigns on gate-level circuit implementations. The methodology is able to deal with the pa...
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