Search For:

Displaying 1-11 out of 11 total
Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking
Found in: VLSI Test Symposium, IEEE
By Chunsheng Liu, Vikram Iyengar, Jiangfan Shi, Erika Cota
Issue Date:May 2005
pp. 349-354
Network-on-Chip is the new paradigm in core-based system design. Reuse of the on-chip communication network for NoC test is critical to reduce test cost. However, efficient reuse of the communication network for test of legacy cores is challenging. A misma...
 
Improving yield of torus nocs through fault-diagnosis-and-repair of interconnect faults
Found in: On-Line Testing Symposium, IEEE International
By Caroline Concatto, Pedro Almeida, Fernanda Kastensmidt, Erika Cota, Marcelo Lubaszewski, Marcos Herve
Issue Date:June 2009
pp. 61-66
We propose a fault tolerance method for torus NoCs capable of increase the yield with minimal performance overhead. The proposed approach consists in detecting and diagnosing interconnect faults using BIST structures and activating alternative paths for th...
 
Diagnosis of interconnect shorts in mesh NoCs
Found in: Networks-on-Chip, International Symposium on
By Marcos Herve, Erika Cota, Fernanda Lima Kastensmidt, Marcelo Lubaszewski
Issue Date:May 2009
pp. 256-265
We propose a method to diagnose interconnect short-circuit faults in mesh 7oCs. The fault model comprises all shorts between any two wires of a defined 7oC neighborhood. Test sequences are applied in 7oC functional mode. Experimental results show that 93% ...
 
Improving the Test of NoC-Based SoCs with Help of Compression Schemes
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Julien Dalmasso, Érika Cota, Marie-Lise Flottes, Bruno Rouzeyre
Issue Date:April 2008
pp. 139-144
Re-using the network in a NoC-based system as a test access mechanism is an attractive solution as pointed out by several authors. As a consequence, testing of NoC-based SoCs is becoming a new challenge for designers. However, the effectiveness of testing ...
 
Power-aware NoC Reuse on the Testing of Core-based Systems
Found in: Test Conference, International
By Érika Cota, Luigi Carro, Flávio Wagner, Marcelo Lubaszewski
Issue Date:October 2003
pp. 612
This work discusses the impact of power consumption on the test time of core-based systems, when an available on-chip network is reused as test access mechanism. A previously proposed technique for the reuse of an on-chip network is extended to consider po...
 
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filter
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Érika Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski
Issue Date:March 2000
pp. 226
The objective of this paper is to discuss the possibility of reusing the existing hardware originally present in an analog application to implement test functions for a completely autonomous self-testable solution. In this first approach, a 8th analog line...
 
Crosstalk- and SEU-Aware Networks on Chips
Found in: IEEE Design and Test of Computers
By Arthur Pereira Frantz, Maico Cassel, Fernanda Lima Kastensmidt, Érika Cota, Luigi Carro
Issue Date:July 2007
pp. 340-350
This article proposes the use of mixed hardware-software solutions to simultaneously address crosstalk faults and single-event upsets in on-chip networks. After analyzing the susceptibility of routers to these faults, the authors propose a software-based s...
 
Test Scheduling for Network-on-Chip with BIST and Precedence Constraints
Found in: Test Conference, International
By Chunsheng Liu, Hamid Sharif, Erika Cota, D.K. Pradhan
Issue Date:October 2004
pp. 1369-1378
Network-on-a-Chip (NoC) is becoming a promising paradigm of core-based system. In this paper, we propose a new method for test scheduling in NoC. The mehod is based on the use of a dedicated routing path for the rest of each core. We show that test schedul...
 
Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router
Found in: Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes (SBCCI '09)
By Altamiro Susin, Caroline Concatto, Debora Matos, Erika Cota, Fernanda Kastensmidt, Luigi Carro, Marcio Kreutz
Issue Date:August 2009
pp. 1-6
As the complexity of designs increase and technologies scale down, devices are subject to new types of malfunctions and failures. Network-on-chip routers are responsible to ensure the proper communication of on-chip cores, and the buffers present in the ro...
     
Reducing test time with processor reuse in network-on-chip based systems
Found in: Proceedings of the 17th symposium on Integrated circuits and system design (SBCCI '04)
By Erika Cota, Alexandre M. Amory, Fernando G. Moraes, Marcelo Lubaszewski
Issue Date:September 2004
pp. 111-116
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores embedded into a system on chip. The resulting test time of the system is eva...
     
Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST
Found in: Proceedings of the 17th symposium on Integrated circuits and system design (SBCCI '04)
By Antonio Andrade, Erika Cota, Marcelo Lubaszewski
Issue Date:September 2004
pp. 105-110
Analog BIST and SoC testing are two topics that have been extensively, but independently, studied in the last few years. However, current mixed-signals systems require the combination of these subjects to generate a cost-effective test solution for the who...
     
 1