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Displaying 1-9 out of 9 total
On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits
Found in: Computer-Aided Design, International Conference on
By Enrique San Millán, Luis Entrena, José Alberto Espejo
Issue Date:November 2001
pp. 91
This paper attempts to determine the capabilities of existing Redundancy Addition and Removal (SRAR) techniques for logic optimization of sequential circuits. To this purpose, we compare this method with the Retiming and Resynthesis (RaR) techniques. For t...
 
AKARI-X: A pseudorandom number generator for secure lightweight systems
Found in: On-Line Testing Symposium, IEEE International
By Honorio Martin,Enrique San Millan,Luis Entrena,Pedro Peris Lopez,Julio Cesar Hernandez Castro
Issue Date:July 2011
pp. 228-233
In order to obtain more secure and reliable systems, the vast majority of RFID protocols include a Pseudorandom Number Generator (PRNG) in its design. However, the authors often do not specify the PRNG to use and standard solutions exceed the capabilities ...
 
Robust cryptographic ciphers with on-line statistical properties validation
Found in: On-Line Testing Symposium, IEEE International
By Anna Vaskova, Celia Lopez-Ongil, Alejandro Jimenez-Horas, Enrique San Millan, Luis Entrena
Issue Date:July 2010
pp. 208-210
A new solution is presented for fast measuring of randomness properties of cryptographic algorithms. Statistical Tests from NIST are hardware implemented in order to enable an on-line detection of intentional attacks in cryptographic ciphers. The small are...
 
Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers
Found in: On-Line Testing Symposium, IEEE International
By Alejandro Jimenez-Horas, Enrique San Millan, Celia Lopez-Ongil, Marta Portela-Garcia, Mario Garcia-Valderas, Luis Entrena
Issue Date:June 2009
pp. 203-205
Latest mitigation techniques proposed at register-transfer level for dependable cryptosystems deal with time redundancy in an active on-line error-detection scheme. Round-based block ciphers are very likely to be hardened with these techniques. Although go...
 
Logic Transformations by Multiple Wire Network Addition
Found in: Digital Systems Design, Euromicro Symposium on
By Enrique San Millán, Luis A. Entrena, José A. Espejo
Issue Date:September 2008
pp. 779-786
This paper presents an important improvement in the current capabilities of existing Redundancy Addition and Removal (RAR) techniques for digital circuits logic optimization. In this work we present a new efficient way of finding all the possible logic add...
 
Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard
Found in: On-Line Testing Symposium, IEEE International
By Celia López-Ongil, Alejandro Jiménez-Horas, Marta Portela-García, Mario García-Valderas, Enrique San Millán, Luis Entrena
Issue Date:July 2008
pp. 167-168
Encryption algorithms could suffer fault injection attacks in order to obtain the secret key. In this paper, a specific protection for any round-based encryption algorithm is presented, analyzed and tested. It is providing a high degree of robustness toget...
 
On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization
Found in: Digital Systems Design, Euromicro Symposium on
By Enrique San Millán, Luis Entrena, José Alberto Espejo
Issue Date:September 2001
pp. 0292
Abstract: This paper attempts to determine the capabilities of existing Redundancy Addition and Removal (SRAR) techniques for logic optimization of sequential circuits. To this purpose, we compare this method with the Retiming and Resynthesis (RaR) techniq...
 
Logic Optimization of Unidirectional Circuits with Structural Methods
Found in: On-Line Testing Workshop, IEEE International
By Luis Entrena, Celia López, Emilio Olías, Enrique San Millán, José A. Espejo
Issue Date:July 2001
pp. 0043
Abstract: Self-checking design based on unordered codes requires that the target circuit is transformed into an unidirectional circuit. Techniques for the design of unidirectional circuits have been proposed. However, in general, multilevel logic optimizat...
 
Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Enrique San Millán, Luis Entrena, José A. Espejo, Silvia Chiusano, Fulvio Corno
Issue Date:March 1999
pp. 516
This paper presents a new integrated approach to logic optimization for sequential circuits. The approach is based on the Redundancy Addition and Removal algorithm, which is based on Automatic Test Pattern Generation (ATPG) techniques, and improves it usin...
 
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