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Displaying 1-50 out of 106 total
Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation
Found in: IEEE Design and Test of Computers
By Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Issue Date:April 2000
pp. 74-85
<p>This article presents a methodology for automatic memory hierarchy generation that exploits memory access locality of embedded software. The methodology is successfully applied to the design of an MP3 decoder.</p>
 
Guest Editor's Introduction: Dynamic Power Management of Electronic Systems
Found in: IEEE Design and Test of Computers
By Enrico Macii
Issue Date:March 2001
pp. 6-9
No summary available.
 
Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction
Found in: Low Power Electronics and Design, International Symposium on
By Ashoka Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Issue Date:August 2008
pp. 51-56
Row-based power-gating has recently emerged as a meet-in-the-middle sleep transistor insertion paradigm between cell-level and block-level granularity, in which each layout row defines the unit of gating, and different rows can be clustered and share the s...
 
Post-Layout Leakage Power Minimization Based on Distributed Sleep Transistor Insertion
Found in: Low Power Electronics and Design, International Symposium on
By Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii
Issue Date:August 2004
pp. 138-143
This paper introduces a new approach to sub-threshold leakage power reduction in CMOS circuits. Our technique is based on automatic insertion of sleep transistors for cutting sub-threshold current when CMOS gates are in stand-by mode. Area and speed overhe...
 
Discharge Current Steering for Battery Lifetime Optimization
Found in: IEEE Transactions on Computers
By Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii, Massimo Poncino
Issue Date:August 2003
pp. 985-995
<p><b>Abstract</b>—Portable and wearable computers can be powered by different combinations of two or more battery packs to give the user the possibility of choosing an optimal compromise between lifetime and weight/size. Recent work on b...
 
Energy-Aware Design Techniques for Differential Power Analysis Protection
Found in: Design Automation Conference
By Luca Benini, Alberto Macii, Enrico Macii, Elvira Omerbegovic, Massimo Poncino, Fabrizio Pro
Issue Date:June 2003
pp. 36
Differential power analysis is a very effective cryptanalysis technique that extracts information on secret keys by monitoring instantaneous power consumption of cryptoprocessors. To protect against differential power analysis, power supply noise is added ...
 
A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Alberto Macii, Enrico Macii, Fabrizio Crudo, Roberto Zafalon
Issue Date:March 2003
pp. 10024
This paper presents a new algorithm for on-the-fly data compression in high performance VLIW processors. The algorithm aggressively targets energy minimization of some of the dominant factors in the SoC energy budget (i.e., main memory access and high thro...
 
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits
Found in: Digital Systems Design, Euromicro Symposium on
By Enrico Macii, Leticia Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino
Issue Date:September 2008
pp. 298-303
Clock Gating and Power Gating are two of the most effective techniques that are applied today for reducing dynamic and leakage power, respectively, in digital CMOS circuits. The combined use of the two solutions, however, poses some challenges in terms of ...
 
Timing-driven row-based power gating
Found in: Low Power Electronics and Design, International Symposium on
By Ashoka Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Issue Date:August 2007
pp. 104-109
In this paper we focus on leakage reduction through automatic insertion of sleep transistors using a row-based granularity. In particular, we tackle here the two main issues involved in this methodology: (i) Clustering and (ii) the interfacing of power-gat...
 
Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Luca Benini, Alessandro Ivaldi, Alberto Macii, Enrico Macii
Issue Date:February 2004
pp. 10698
In this paper, we propose a combined solution that allows us to customize the architecture of internally partitioned SRAM macros according to the given application be executed. Energy savings with respect to monolithic memory configurations are above 40%, ...
   
Improving the Efficiency of Memory Partitioning by Address Clustering
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Alberto Macii, Enrico Macii, Massimo Poncino
Issue Date:March 2003
pp. 10018
<p>Memory partitioning is an effective approach to memory energy optimization in embedded systems. Spatial locality of the memory address profile is the key property that partitioning exploits to determine an efficient multi-bank memory architecture....
 
Hardw are Implementation of Data Compression Algorithms for Memory Energy Optimization
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii
Issue Date:February 2003
pp. 250
This paper describes implementation details of a hardware compression and decompression unit (CDU) for optimizing energy consumption in processor-based systems. Many algorithms for data compression (i.e., profile-driven, adaptive, differential) have been i...
   
Battery-Driven Dynamic Power Management of Portable Systems
Found in: System Synthesis, International Symposium on
By Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Riccardo Scarsi
Issue Date:September 2000
pp. 25
Battery lifetime extension is a primary design objective for portable systems. Traditionally, mainly reducing average power consumption of system components has prolonged battery lifetime. A careful analysis of discharge characteristics and the adoption of...
 
Synthesis of Application-Specific Memories for Power Optimization in Embedded Systems
Found in: Design Automation Conference
By Alberto Macii, Massimo Poncino, Enrico Macii, Luca Benini
Issue Date:June 2000
pp. 300-303
This paper presents a novel approach to memory power optimization for embedded systems based on the exploitation of data locality. Locations with highest access frequency are mapped onto a small, low-power application-specific memory which is placed close ...
 
Region Compression: A New Scheme for Memory Energy Minimization in Embedded Systems
Found in: EUROMICRO Conference
By Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Issue Date:September 1999
pp. 1311
Power consumption in microprocessor-based embedded systems can be reduced by decreasing the number of memory accesses needed to fetch instructions from memory. We propose a code compression approach that reduces instruction memory bandwidth by assigning sh...
 
RTL Power Estimation in an Industrial Design Flow
Found in: Low-Power Design, IEEE Alessandro Volta Memorial Workshop on
By Carlo Guardiani, Massimo Rossello, Roberto Zafalon, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi, Cristina Silvano
Issue Date:March 1999
pp. 91
In this work, we analyze the integration of an RT-level power estimation tool, RTPOW, into an industrial design flow. In particular, we address important practical issues like the extraction of structural and functional information, as well as the use of s...
 
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
Found in: Great Lakes Symposium on VLSI
By Luca Benini, Giovanni de Micheli, Alberto Macii, Enrico Macii, Massimo Poncino
Issue Date:February 1998
pp. 8
With the increased clock frequency of modern, high-performance processors (over 500 MHz, in some cases), limiting the power dissipation has become the most stringent design target. It is thus mandatory for processor engineers to resort to a large variety o...
 
Gelsius: A Literature-Based Workflow for Determining Quantitative Associations between Genes and Biological Processes
Found in: IEEE/ACM Transactions on Computational Biology and Bioinformatics
By Francesco Abate,Andrea Acquaviva,Elisa Ficarra,Roberto Piva,Enrico Macii
Issue Date:May 2013
pp. 619-631
An effective knowledge extraction and quantification methodology from biomedical literature would allow the researcher to organize and analyze the results of high-throughput experiments on microarrays and next-generation sequencing technologies. Despite th...
 
Motion Artifact Correction in ASL images: An Improved Automated Procedure
Found in: Bioinformatics and Biomedicine, IEEE International Conference on
By Santa Di Cataldo,Elisa Ficarra,Andrea Acquaviva,Enrico Macii
Issue Date:November 2011
pp. 410-413
Arterial Spin Labelling (ASL) is a perfusion MRI technique with tremendous applications in the study of biological markers and prognostic factors of brain tumors and in the assessment of neural diseases, moreover, it is completely non-invasive as it uses t...
 
A novel framework for chimeric transcript detection based on accurate gene fusion model
Found in: Bioinformatics and Biomedicine Workshop, IEEE International Conference on
By Francesco Abate,Andrea Acquaviva,Elisa Ficarra,Giulia Paciello,Enrico Macii,Alberto Ferrarini,Massimo Delledonne,Simona Soverini,Giovanni Martinelli
Issue Date:November 2011
pp. 34-41
Next generation sequencing plays a key role in the detection of structural variations. Chimeric transcripts are relevant examples of such variations, as they are involved in several diseases. In this work, we propose an effective methodology for the detect...
 
Adaptive Task Migration Policies for Thermal Control in MPSoCs
Found in: VLSI, IEEE Computer Society Annual Symposium on
By David Cuesta, José L. Ayala, José I. Hidalgo, David Atienza, Andrea Acquaviva, Enrico Macii
Issue Date:July 2010
pp. 110-115
In deep submicron circuits, high temperatures have created critical issues in reliability, timing, performance, coolings costs and leakage power. Task migration techniques have been proposed to manage efficiently the thermal distribution in multi-processor...
 
Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Subbanking
Found in: IEEE Transactions on Computers
By Mirko Loghi, Olga Golubeva, Enrico Macii, Massimo Poncino
Issue Date:July 2010
pp. 891-904
Partitioning a memory into multiple blocks that can be independently accessed is a widely used technique to reduce its dynamic power. For embedded systems, its benefits can be even pushed further by properly matching the partition to the memory access patt...
 
NBTI-aware power gating for concurrent leakage and aging optimization
Found in: Low Power Electronics and Design, International Symposium on
By Andrea Calimera, Enrico Macii, Massimo Poncino
Issue Date:August 2009
pp. 127-132
Power and reliability are known to be intrinsically conflicting metrics: traditional solutions to improve reliability such as redundancy, increase of voltage levels, and up-sizing of critical devices do contrast with traditional low-power solutions, which ...
 
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits
Found in: Low Power Electronics and Design, International Symposium on
By Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino
Issue Date:August 2008
pp. 217-220
The effects of temperature on delay depend on several parameters, such as cell size, load, supply voltage, and threshold voltage. In particular, variations in Vth can yield a temperature inversion effect causing a decreases of cell delay as temperature inc...
 
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Andrea Calimera, Luca Benini, Enrico Macii
Issue Date:March 2008
pp. 973-978
Sleep transistor insertion is one of today's most promising and widely adopted solutions for controlling stand-by leakage power in nanometer circuits. Although single-cycle power mode transition reduces wake-up latency, it originates large discharge curren...
 
Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Bonesi Stefano, Davide Bertozzi, Luca Benini, Enrico Macii
Issue Date:March 2008
pp. 967-972
A common technique to compensate process variation induced performance deviations during post-silicon testing consists of the dynamic adaptation of processor voltage. This however comes at a significant power cost. We envision multi supply voltage design (...
 
Selection of Tumor Areas and Segmentation of Nuclear Membranes in Tissue Confocal Images: A Fully Automated Approach
Found in: Bioinformatics and Biomedicine, IEEE International Conference on
By Santa Di Cataldo, Elisa Ficarra, Enrico Macii
Issue Date:November 2007
pp. 390-398
An accurate and standardized technique for tumor tissue segmentation is a critical step for monitoring and quantifying the activity of specific families of pro- teins involved in multi-factorial genetic pathologies. However, fully automated tissue and cell...
 
Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies
Found in: Low Power Electronics and Design, International Symposium on
By Simone Medardoni, Davide Bertozzi, Enrico Macii
Issue Date:August 2007
pp. 159-164
With the advent of nanoscale technologies, developing power efficient ASICs increasingly requires consideration of static power. An effective approach to make RTL synthesis algorithms and tools leakage-aware consists of the smart inference of RTL macros ba...
 
Locality-driven architectural cache sub-banking for leakage energy reduction
Found in: Low Power Electronics and Design, International Symposium on
By Olga Golubeva, Mirko Loghi, Enrico Macii, Massimo Poncino
Issue Date:August 2007
pp. 274-279
In most processors, caches account for the largest fraction of onchip transistors, thus being a primary candidate for tackling the leakage problem. Existing architectural solutions usually rely on customized cache structures, which are needed to implement ...
 
Mining Gene Sets for Measuring Similarities
Found in: Computers and Communications, IEEE Symposium on
By Christine Nardini, Daniele Masotti, Sungroh Yoon, Enrico Macii, Michael D. Kuo, Giovanni De Micheli, Luca Benini
Issue Date:June 2006
pp. 227-232
In recent years, the development of high throughput devices for the massive parallel analyses of genomic data has lead to the generation of large amount of new biological evidences and has triggered the proliferation of data mining algorithms for the extra...
 
Computer-Aided Evaluation of Protein Expression in Pathological Tissue Images
Found in: Computer-Based Medical Systems, IEEE Symposium on
By Elisa Ficarra, Enrico Macii, Giovanni De Micheli, Luca Benini
Issue Date:June 2006
pp. 413-418
This work presents the first fully-automated computeraided analysis approach to the quantification of the expression of receptors for the non-small cell lung carcinoma. This immunohistochemical analysis is usually performed by pathologists via visual inspe...
 
Energy-Efficient Color Approximation for Digital LCD Interfaces
Found in: Computer Design, International Conference on
By Andi Nourrachmat, Sabino Salerno, Enrico Macii, Massimo Poncino
Issue Date:October 2005
pp. 81-86
<p>The limited resolution capabilities of color displays, coupled with the limited perceptual resolution of the human eye has been exploited to reduce the actual number of colors that are simultaneously displayed. In this work, we propose a color app...
 
Limited Intra-Word Transition Codes: An Energy-Efficient Bus Encoding for LCD Display Interfaces
Found in: Low Power Electronics and Design, International Symposium on
By Sabino Salerno, Alberto Bocca, Enrico Macii, Massimo Poncino
Issue Date:August 2004
pp. 206-211
We propose a class of low-power codes, called Limited Intra-Word Transition (LIWT) codes, suitable for the digital interface to Liquid Crystal Displays (LCD).<div></div> The proposed technique exploits the existing inter-pixel correlation of ty...
 
Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Kimish Patel, Enrico Macii, Massimo Poncino
Issue Date:February 2004
pp. 10700
<p>Accesses to the shared memory in multi-processor systems-on-chip represent a significant performance bottleneck. Multi-port memories are a common solution to this problem, because they allow to parallelize accesses. However, they are not an energy...
   
Clock-Tree Power Optimization based on RTL Clock-Gating
Found in: Design Automation Conference
By Monica Donno, Alessandro Ivaldi, Luca Benini, Enrico Macii
Issue Date:June 2003
pp. 622
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing clock power based on clock gating. We present a methodology that, starting from...
 
On-the-Fly Layout Generation for PTL Macrocells
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Luca Macchiarulo, Enrico Macii, Luca Benini
Issue Date:March 2001
pp. 0546
Abstract: Pass transistor logic (PTL) has been recently proposed as an alternative to standard MOS for aggressive circuit design. Even though PTL has been successful in a few handcrafted designs, its acceptance into mainstream digital design critically dep...
 
Clustered Table-Based Macromodels for RTL Power Estimation
Found in: Great Lakes Symposium on VLSI
By Roberto Corgnati, Enrico Macii, Massimo Poncino
Issue Date:March 1999
pp. 354
Macromodeling is considered the most effective approach to RTL power estimation. Among the macromodels presented in the literature, table-based ones have overcome some of the limitations of conventional, equation-based solutions. In this paper we propose s...
 
Power Estimation of Behavioral Descriptions
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino
Issue Date:February 1998
pp. 762
This paper presents a methodology for power estimation of designs described at the behavioral-level as the interconnection of functional modules. The input/output behavior of each module is implicitly stored using BDDs, and the power consumed by the networ...
 
Address Bus Encoding Techniques for System-Level Power Optimization
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Luca Benini, Giovanni de Micheli, Donatella Sciuto, Enrico Macii, Cristina Silvano
Issue Date:February 1998
pp. 861
The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I/O interfaces can provide significant savings on the overall power budget. Th...
 
Testing Core-Based Systems: A Symbolic Methodology
Found in: IEEE Design and Test of Computers
By Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto, Enrico Macii, Massimo Poncino
Issue Date:October 1997
pp. 69-77
One of the primary draw-backs of the core-based design paradigm is the limited knowledge of the internal structure and organization of the cores which is provided to the users. This problem is particularly critical from the point of view of testing, since ...
 
Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems
Found in: Great Lakes Symposium on VLSI
By Luca Benini, Giovanni de Micheli, Enrico Macii, Donatella Sciuto, Cristina Silvano
Issue Date:March 1997
pp. 77
In microprocessor-based systems, large power savings can be achieved through reduction of the transition activity of the on- and off-chip busses. This is because the total capacitance being switched when a voltage change occurs on a bus line is usually sen...
 
Accurate Entropy Calculation for Large Logic Circuits Based on Output Clustering
Found in: Great Lakes Symposium on VLSI
By Antonio Lioy, Enrico Macii, Massimo Poncino, Massimo Rossello
Issue Date:March 1997
pp. 70
Entropy-based estimation is a promising approach to the problem of predicting the power dissipated by a digital system for which an architectural description is available. For achieving good performance of the power estimation tool, an accurate computation...
 
Enhancing FSM Traversal by Temporary Re-Encoding
Found in: Computer Design, International Conference on
By Gianpiero Cabodi, Luciano Lavagno, Enrico Macii, Massimo Poncino, Stefano Quer, Paolo Camurati, Ellen Sentovicha
Issue Date:October 1996
pp. 6
Synthesis and optimization of large finite--state machines has improved dramatically over the last few years with the introduction and rapid improvement of symbolic--state manipulation techniques. The algorithms efficiently visit each reachable state in th...
 
BDD-Based Testability Estimation of VHDL Designs
Found in: European Design Automation Conference with EURO-VHDL
By Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto
Issue Date:September 1996
pp. 0444
In this paper we present a method, based on symbolic ATPG techniques, that allows the designer to predict the testability of a control-oriented complex design specified as a set of interacting VHDL modules. Conversely from existing approaches, our method i...
 
Exact Computation of the Entropy of a Logic Circuit
Found in: Great Lakes Symposium on VLSI
By Enrico Macii, Massimo Poncino
Issue Date:March 1996
pp. 162
Computing the entropy of a digital circuit has proved to be very useful for several applications in the area of VLSI system design. Recently, a method for entropy calculation has been used in the context of power estimation for logic circuits described at ...
 
Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction
Found in: Proceeding of the thirteenth international symposium on Low power electronics and design (ISLPED '08)
By Alberto Macii, Ashoka Sathanur, Enrico Macii, Luca Benini, Massimo Poncino
Issue Date:August 2008
pp. 383-384
Row-based power-gating has recently emerged as a meet-in-the-middle sleep transistor insertion paradigm between cell-level and block-level granularity, in which each layout row defines the unit of gating, and different rows can be clustered and share the s...
     
Optimal sleep transistor synthesis under timing and area constraints
Found in: Proceedings of the 18th ACM Great Lakes symposium on VLSI (GLSVLSI '08)
By Alberto Macii, Antonio Pullini, Ashoka Sathanur, Enrico Macii, Luca Benini, Massimo Poncino
Issue Date:May 2008
pp. 1-37
Leakage power reduction in nano-CMOS designs has gained tremendous interest both in academia and industry. Many techniques have been proposed in the literature for leakage power reduction and one of the prominent techniques for leakage power reduction is t...
     
Timing-driven row-based power gating
Found in: Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)
By Alberto Macii, Antonio Pullini, Ashoka Sathanur, Enrico Macii, Luca Benini, Massimo Poncino
Issue Date:August 2007
pp. 104-109
In this paper we focus on leakage reduction through automatic insertion of sleep transistors using a row-based granularity. In particular, we tackle here the two main issues involved in this methodology: (i) Clustering and (ii) the interfacing of power-gat...
     
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology
Found in: Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI (GLSVLSI '07)
By Alberto Macii, Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Enrico Macii, Luca Benini, Massimo Poncino
Issue Date:March 2007
pp. 501-504
Clustered sleep transistor insertion is an effective leakage power reduction technique that is well-suited for integration in an automated design flow and offers a flexible tradeoff between area, delay overhead and turn-on transition time. In this work, we...
     
Post-layout leakage power minimization based on distributed sleep transistor insertion
Found in: Proceedings of the 2004 international symposium on Low power electronics and design (ISLPED '04)
By Alberto Macii, Enrico Macii, Luca Benini, Pietro Babighian
Issue Date:August 2004
pp. 138-143
This paper introduces a new approach to sub-threshold leakage power reduction in CMOS circuits. Our technique is based on automatic insertion of sleep transistors for cutting sub-threshold current when CMOS gates are in stand-by mode. Area and speed overhe...
     
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