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Displaying 1-18 out of 18 total
Phase change memory architecture and the quest for scalability
Found in: Communications of the ACM
By Benjamin C. Lee, Doug Burger, Doug Burger, Doug Burger, Engin Ipek, Engin Ipek, Engin Ipek, Onur Mutlu, Onur Mutlu, Onur Mutlu
Issue Date:July 2010
pp. 99-106
Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as dynamic random access memory (DRAM). In contrast, phase change memory (PCM) relies on programmable resistances, as well a...
     
Phase-Change Technology and the Future of Main Memory
Found in: IEEE Micro
By Benjamin C. Lee, Ping Zhou, Jun Yang, Youtao Zhang, Bo Zhao, Engin Ipek, Onur Mutlu, Doug Burger
Issue Date:January 2010
pp. 143-143
<p>Phase-change memory may enable continued scaling of main memories, but PCM has higher access latencies, incurs higher power costs, and wears out more quickly than DRAM. This article discusses how to mitigate these limitations through buffer sizing...
 
Programmable DDRx Controllers
Found in: IEEE Micro
By Mahdi Nazm Bojnordi,Engin Ipek
Issue Date:May 2013
pp. 106-115
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatil...
 
Dynamic Multicore Resource Management: A Machine Learning Approach
Found in: IEEE Micro
By José F. Martínez, Engin İpek
Issue Date:September 2009
pp. 8-17
<p>A machine learning approach to multicore resource management produces self-optimizing on-chip hardware agents capable of learning, planning, and continuously adapting to changing workload demands. This results in more efficient and flexible manage...
 
Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Ramazan Bitirgen, Engin Ipek, Jose F. Martinez
Issue Date:November 2008
pp. 318-329
Efficient sharing of system resources is critical to obtaining high utilization and enforcing system-level performance objectives on chip multiprocessors (CMPs). Although several proposals that address the management of a single microarchitectural resource...
 
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach
Found in: Computer Architecture, International Symposium on
By Engin Ipek, Onur Mutlu, José F. Martínez, Rich Caruana
Issue Date:June 2008
pp. 39-50
Efficiently utilizing off-chip DRAM bandwidth is a critical issuein designing cost-effective, high-performance chip multiprocessors(CMPs). Conventional memory controllers deliver relativelylow performance in part because they often employ fixed,rigid acces...
 
A Reconfigurable Chip Multiprocessor Architecture to Accommodate Software Diversity
Found in: Parallel and Distributed Processing Symposium, International
By Engin Ipek, Meyrem Kirman, Nevin Kirman, Jose F. Martinez
Issue Date:March 2007
pp. 338
We present core fusion, a reconfigurable chip multiprocessor (CMP) architecture where groups of fundamentally independent cores can dynamically morph into a larger CPU, or they can be used as distinct processing elements, as needed at run time by applicati...
 
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor
Found in: Dependable Systems and Networks, International Conference on
By Christopher LaFrieda, Engin Ipek, Jose F. Martinez, Rajit Manohar
Issue Date:June 2007
pp. 317-326
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Existing fault-tolerant CMP proposals that implement dual modular redundancy (DMR...
 
A programmable memory controller for the DDRx interfacing standards
Found in: ACM Transactions on Computer Systems (TOCS)
By Mahdi Nazm Bojnordi, Engin Ipek
Issue Date:December 2013
pp. 1-31
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatil...
     
DESC: energy-efficient data exchange using synchronized counters
Found in: Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46)
By Engin Ipek, Mahdi Nazm Bojnordi
Issue Date:December 2013
pp. 234-246
Increasing cache sizes in modern microprocessors require long wires to connect cache arrays to processor cores. As a result, the last-level cache (LLC) has become a major contributor to processor energy, necessitating techniques to increase the energy effi...
     
AC-DIMM: associative computing with STT-MRAM
Found in: Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA '13)
By Eby G. Friedman, Engin Ipek, Qing Guo, Ravi Patel, Xiaochen Guo
Issue Date:June 2013
pp. 189-200
With technology scaling, on-chip power dissipation and off-chip memory bandwidth have become significant performance bottlenecks in virtually all computer systems, from mobile devices to supercomputers. An effective way of improving performance in the face...
     
PARDIS: a programmable memory controller for the DDRx interfacing standards
Found in: Proceedings of the 39th Annual International Symposium on Computer Architecture (ISCA '12)
By Engin Ipek, Mahdi Nazm Bojnordi
Issue Date:June 2012
pp. 13-24
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatil...
     
A resistive TCAM accelerator for data-intensive computing
Found in: Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-44 '11)
By Engin Ipek, Qing Guo, Xiaochen Guo, Yuxin Bai
Issue Date:December 2011
pp. 339-350
Power dissipation and off-chip bandwidth restrictions are critical challenges that limit microprocessor performance. Ternary content addressable memories (TCAM) hold the potential to address both problems in the context of a wide range of data-intensive wo...
     
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing
Found in: Proceedings of the 37th annual international symposium on Computer architecture (ISCA '10)
By Engin Ipek, Tolga Soyata, Xiaochen Guo
Issue Date:June 2010
pp. 72-ff
As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations, traditional MOSFET scaling theory prescribes reducing supply and threshold ...
     
Dynamically replicated memory: building reliable systems from nanoscale resistive memories
Found in: Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems (ASPLOS '10)
By Doug Burger, Edmund B. Nightingale, Engin Ipek, Jeremy Condit, Thomas Moscibroda
Issue Date:March 2010
pp. 222-230
DRAM is facing severe scalability challenges in sub-45nm tech- nology nodes due to precise charge placement and sensing hur- dles in deep-submicron geometries. Resistive memories, such as phase-change memory (PCM), already scale well beyond DRAM and are a ...
     
Better I/O through byte-addressable, persistent memory
Found in: Proceedings of the ACM SIGOPS 22nd symposium on Operating systems principles (SOSP '09)
By Benjamin Lee, Christopher Frost, Derrick Coetzee, Doug Burger, Edmund B. Nightingale, Engin Ipek, Jeremy Condit
Issue Date:October 2009
pp. 133-146
Modern computer systems have been built around the assumption that persistent storage is accessed via a slow, block-based interface. However, new byte-addressable, persistent memory technologies such as phase change memory (PCM) offer fast, fine-grained ac...
     
Architecting phase change memory as a scalable dram alternative
Found in: Proceedings of the 36th annual international symposium on Computer architecture (ISCA '09)
By Benjamin C. Lee, Doug Burger, Engin Ipek, Onur Mutlu
Issue Date:June 2009
pp. 70-73
Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as DRAM. In contrast, phase change memory (PCM) storage relies on scalable current and thermal mechanisms. To exploit PCM's ...
     
Core fusion: accommodating software diversity in chip multiprocessors
Found in: Proceedings of the 34th annual international symposium on Computer architecture (ISCA '07)
By Engin Ipek, Jose F. Martinez, Meyrem Kirman, Nevin Kirman
Issue Date:June 2007
pp. 186-197
This paper presents core fusion, a reconfigurable chip multiprocessor(CMP) architecture where groups of fundamentally independent cores can dynamically morph into a larger CPU, or they can be used as distinct processing elements, as needed at run time by a...
     
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