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Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?
Found in: On-Line Testing Symposium, IEEE International
By Abhijit Chatterjee, Jacob Abraham, Adit Singh, Elie Maricau, Rakesh Kumar, Christos Papachristou
Issue Date:June 2009
pp. 129
There has been ongoing debate regarding the use of voltage overscaling along with error resilience techniques for ultra low power operation of scaled CMOS logic. The issue is whether to build enough design margin into future electronic systems so that erro...
 
A methodology for measuring transistor ageing effects towards accurate reliability simulation
Found in: On-Line Testing Symposium, IEEE International
By Elie Maricau, Georges Gielen
Issue Date:June 2009
pp. 21-26
Emerging die-level stress effects (i.e. NBTI, HCI, TDDB, etc.) in nanometer CMOS technologies cause both analog and digital circuit parameters to degrade over time. To efficiently evaluate these degradation effects in modern ICs, a reliability simulator, u...
 
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