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Displaying 1-9 out of 9 total
Derivation of optimum test sequencies for sequential machines
Found in: Foundations of Computer Science, Annual IEEE Symposium on
By J. F. Poage, E. J. McCluskey
Issue Date:November 1964
pp. 121-132
A technique is presented for deriving the shortest sequence of input symbols which must be applied to a sequential machine to guarantee that no fault from a set {p} exists within the machine. Flow tables are used to describe the machine for which a test is...
 
Encoding of Incompletely Specified Boolean Matrices
Found in: Managing Requirements Knowledge, International Workshop on
By T. A. Dolotta, E. J. McCluskey, Jr.
Issue Date:May 1960
pp. 231
No summary available.
   
Diagnosis of Sequence-Dependent Chips
Found in: VLSI Test Symposium, IEEE
By James C.-M. Li, E. J. McCluskey
Issue Date:May 2002
pp. 0187
A technique capable of diagnosing single and multiple stuck-open and stuck-at faults is presented. Eleven sequence-dependent chips (test results depend on the order of test patterns) are diagnosed. Seven of them are diagnosed as having single stuck-open fa...
 
Logical design theory of NOR gate networks with no complemented inputs
Found in: Foundations of Computer Science, Annual IEEE Symposium on
By E. J. McCluskey
Issue Date:October 1963
pp. 137-148
It can he easily shown that any combinational circuit with only uncomplemented inputs can be realized using three stages of NOR logic. However, if such a circuit is designed by a direct extension of the theory of two-stage circuits using AND Gates and OR G...
 
ELF-Murphy Data on Defects and Test Sets
Found in: VLSI Test Symposium, IEEE
By E. J. McCluskey, Ahmad Al-Yamani, James C.-M Li, Chao-Wen Tseng, Erik Volkerink, Francois-Fabien Ferhani, Edward Li, Subhasish Mitra
Issue Date:April 2004
pp. 16
We at CRC have designed and LSI Logic has manufactured two test chip designs;these were used to investigate the characteristics of actual production defects and the effectiveness of various test techniques in detecting their presence. This paper presents a...
 
Analysis And Detection of Timing Failures In An Experimental Test Chip
Found in: Test Conference, International
By Piero Franco, Siyad Ma, Jonathan Chang, Yi-Chin Chu, Sanjay Wattal, E. J. McCluskey, Robert L. Stokes, William D. Farwell
Issue Date:October 1996
pp. 691
A 25k gate Test Chip was designed and manufactured to evaluate different test methods for scan-designed circuits. The design of the chip, the experiment, and preliminary experimental results were presented at ITC'95. This paper presents results for differe...
 
Reduction of feedback loops in sequential circuits and carry leads in iterative networks
Found in: Foundations of Computer Science, Annual IEEE Symposium on
By E. J. McCluskey
Issue Date:October 1962
pp. 91-102
Techniques are presented for making use of
 
Minimal sums for Boolean functions having many unspecified fundamental products
Found in: Foundations of Computer Science, Annual IEEE Symposium on
By E. J. McCluskey
Issue Date:October 1961
pp. 10-17
Many techniques have been developed for finding minimal sums and minimal products for Boolean functions. In all of these techniques, it is necessary to use either all of the fundamental products which must be included in the function and all of the unspeci...
 
Memorial session for S. H. Caldwell (1904-1960)
Found in: Foundations of Computer Science, Annual IEEE Symposium on
By E. J. McCluskey
Issue Date:October 1961
pp. 113
This paper presents examples illustrative of practical problems encountered in the physical realization of a speed independent control for a high speed computer under construction at the University of Illinois. Three separate problems are described; each i...
 
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