Search For:

Displaying 1-3 out of 3 total
The Fault Attack Jungle - A Classification Model to Guide You
Found in: Fault Diagnosis and Tolerance in Cryptography, Workshop on
By Ingrid Verbauwhede,Duško Karaklajic,Jörn-Marc Schmidt
Issue Date:September 2011
pp. 3-8
For a secure hardware designer, the vast array of fault attacks and countermeasures looks like a jungle. This paper aims at providing a guide through this jungle and at helping a designer of secure embedded devices to protect a design in the most efficient...
Low Cost Built in Self Test for Public Key Crypto Cores
Found in: Fault Diagnosis and Tolerance in Cryptography, Workshop on
By Duško Karaklajic, Miroslav Kneževic, Ingrid Verbauwhede
Issue Date:August 2010
pp. 97-103
The testability of cryptographic cores brings an extra dimension to the process of digital circuits testing security. The benefits of the classical methods such as the scan-chain method introduce new vulnerabilities concerning the data protection. The Buil...
FPGA-based testing strategy for cryptographic chips: A case study on Elliptic Curve Processor for RFID tags
Found in: On-Line Testing Symposium, IEEE International
By Junfeng Fan, Miroslav Knezevic, Dusko Karaklajic, Roel Maes, Vladimir Rozic, Lejla Batina, Ingrid Verbauwhede
Issue Date:June 2009
pp. 189-191
Testing of cryptographic chips or components has one extra dimension: physical security. The chip designers should improve the design if it leaks too much information through side-channels, such as timing, power consumption, electric-magnetic radiation, an...