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Displaying 1-50 out of 113 total
ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon
Found in: IEEE Design and Test of Computers
By Dennis Sylvester, David Blaauw, Eric Karl
Issue Date:November 2006
pp. 484-490
With continued technology scaling, silicon is becoming increasingly less predictable. Recent years have brought an acceleration of wear-out mechanisms, such as oxide breakdown and NBTI, which occur over a part's lifetime. Manufacturing device failure rates...
 
Power-Driven Challenges in Nanometer Design
Found in: IEEE Design and Test of Computers
By Dennis Sylvester, Himanshu Kaul
Issue Date:November 2001
pp. 12-22
<p>Addressing fundamental challenges to designing high-performance ICs in nanometer-scale technologies, the authors advocate a flexible approach to limiting both dynamic and static power. They recommend global-signaling strategies to curb communicati...
 
Reconfigurable energy efficient near threshold cache architectures
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Ronald G. Dreslinski, Gregory K. Chen, Trevor Mudge, David Blaauw, Dennis Sylvester, Krisztian Flautner
Issue Date:November 2008
pp. 459-470
Battery life is an important concern for modern embedded processors. Supply voltage scaling techniques can provide an order of magnitude reduction in energy. Current commercial memory technologies have been limited in the degree of supply voltage scaling t...
 
A statistical approach for full-chip gate-oxide reliability analysis
Found in: Computer-Aided Design, International Conference on
By Kaviraj Chopra, Cheng Zhuo, David Blaauw, Dennis Sylvester
Issue Date:November 2008
pp. 698-705
Gate oxide breakdown is a key factor limiting the useful lifetime of an integrated circuit. Unfortunately, the conventional approach for full chip oxide reliability analysis assumes a uniform oxide-thickness for all devices. In practice, however, gate-oxid...
 
STEEL: A technique for stress-enhanced standard cell library design
Found in: Computer-Aided Design, International Conference on
By Brian T. Cline, Vivek Joshi, Dennis Sylvester, David Blaauw
Issue Date:November 2008
pp. 691-697
Mobility degradation and device scaling limitations have led process engineers to develop new techniques that introduce mechanical stress in MOSFET channels, which results in enhanced carrier transport. New fabrication steps strive to increase carrier mobi...
 
Variation-aware gate sizing and clustering for post-silicon optimized circuits
Found in: Low Power Electronics and Design, International Symposium on
By Cheng Zhuo, David Blaauw, Dennis Sylvester
Issue Date:August 2008
pp. 105-110
As technology is aggressively scaled, nano-regime VLSI designs are becoming increasingly susceptible to process variations. Unlike pre-silicon optimization, post-silicon techniques can tune the individual die to better meet the power-delay constraints. Thi...
 
Fast and Accurate Waveform Analysis with Current Source Models
Found in: Quality Electronic Design, International Symposium on
By Vineeth Veetil, Dennis Sylvester, David Blaauw
Issue Date:March 2008
pp. 53-56
Recently current source models (CSMs) have become popular for use in standard cell characterization and static timing analysis. However, there has not been any detailed study of what aspects of the gate behavior should be modeled for sufficient accuracy, a...
 
Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures
Found in: Quality Electronic Design, International Symposium on
By Eric Karl, Dennis Sylvester, David Blaauw
Issue Date:March 2008
pp. 391-395
Continued technology scaling exacerbates the incidence of degradation and failure in integrated circuits due to mechanisms such as oxide breakdown, negative bias temperature instability and electromigration. This work analyzes the impact of different facto...
 
An Energy Efficient Parallel Architecture Using Near Threshold Operation
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Ronald G. Dreslinkski, Bo Zhai, Trevor Mudge, David Blaauw, Dennis Sylvester
Issue Date:September 2007
pp. 175-188
Subthreshold circuit design, while energy efficient, has the drawback of performance degradation. To retain the excellent energy efficiency while reducing performance loss, we propose to investigate near subthreshold techniques on chip multiprocessors (CMP...
 
Energy efficient near-threshold chip multi-processing
Found in: Low Power Electronics and Design, International Symposium on
By Bo Zhai, Ronald G. Dreslinski, David Blaauw, Trevor Mudge, Dennis Sylvester
Issue Date:August 2007
pp. 32-37
Subthreshold circuit design has become a popular approach for building energy efficient digital circuits. One drawback is performance degradation due to the exponentially reduced driving current. This had limited subthreshold circuits to relatively low per...
 
Power Gating with Multiple Sleep Modes
Found in: Quality Electronic Design, International Symposium on
By Kanak Agarwal, Kevin Nowka, Harmander Deogun, Dennis Sylvester
Issue Date:March 2006
pp. 633-637
This paper describes a power gating technique with multiple sleep modes where each mode represents a trade-off between wake-up overhead and leakage savings. We show that high wake-up latency and wake-up power penalty of traditional power gating limits its ...
 
Logic SER Reduction through Flipflop Redesign
Found in: Quality Electronic Design, International Symposium on
By Vivek Joshi, Rajeev R. Rao, David Blaauw, Dennis Sylvester
Issue Date:March 2006
pp. 611-616
In this paper, we present a new flipflop sizing scheme that efficiently immunizes combinational logic circuits from the effects of radiation induced single event transients (SET). The proposed technique leverages the effect of temporal masking by selective...
 
Performance Driven OPC for Mask Cost Reduction
Found in: Quality Electronic Design, International Symposium on
By Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang
Issue Date:March 2005
pp. 270-275
With continued aggressive process scaling in the subwavelength lithographic regime, resolution enhancement techniques (RETs) such as optical proximity correction (OPC) are an integral part of the design to mask flow. OPC adds complex features to the layout...
 
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Robert Bai, Nam-Sung Kim, Tae Ho Kgil, Dennis Sylvester, Trevor Mudge
Issue Date:March 2005
pp. 650-651
In this paper, we investigate the impact of T_{ox} and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a single level cache and then extend this to two level cache systems. In addi...
   
A New Algorithm for Improved VDD Assignment in Low Power Dual VDD Systems
Found in: Low Power Electronics and Design, International Symposium on
By Sarvesh H. Kulkarni, Ashish N. Srivastava, Dennis Sylvester
Issue Date:August 2004
pp. 200-205
We present the first in-depth study of the two existing algorithms, namely, Clustered Voltage Scaling (CVS) and Extended Clustered Voltage Scaling (ECVS), used for assigning the voltage supply to gates in integrated circuits having dual power supplies. We ...
 
Approaches to Run-Time and Standby Mode Leakage Reduction in Global Buses
Found in: Low Power Electronics and Design, International Symposium on
By Rahul Rao, Kanak Agarwal, Dennis Sylvester, Richard Brown, Kevin Nowka, Sani Nassif
Issue Date:August 2004
pp. 188-193
In this paper, we present various design approaches to leakage minimization in global repeaters. We demonstrate the applicability of the MTCMOS scheme to global repeaters for leakage reduction. We then analyze two design approaches called Duplicated Skewed...
 
Statistical Optimization of Leakage Power Considering Process Variations using Dual-Vth and Sizing
Found in: Design Automation Conference
By Ashish Srivastava, Dennis Sylvester, David Blaauw
Issue Date:June 2004
pp. 773-778
Increasing levels of process variability in sub-100nm CMOS design has become a critical concern for performance and power constraint designs. In this paper, we propose a new statistically aware Dual-Vt and sizing optimization that considers both the variab...
 
Parametric Yield Estimation Considering Leakage Variability
Found in: Design Automation Conference
By Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester
Issue Date:June 2004
pp. 442-447
Leakage current has become a stringent constraint in modern processor designs in addition to traditional constraints on frequency. Since leakage current exhibits a strong inverse correlation with circuit delay, effective parametric yield prediction must co...
 
Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Control
Found in: Design Automation Conference
By Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester
Issue Date:June 2004
pp. 327-330
With process scaling, leakage power reduction has become one of the most important design concerns. Multi-threshold techniques have been used to reduce runtime leakage power without sacrificing performance. In this paper, we propose small biases of transis...
 
Theoretical and Practical Limits of Dynamic Voltage Scaling
Found in: Design Automation Conference
By Bo Zhai, David Blaauw, Dennis Sylvester, Krisztian Flautner
Issue Date:June 2004
pp. 868-873
Dynamic voltage scaling (DVS) is a popular approach for energy reduction of integrated circuits. Current processors that use DVS typically have an operating voltage range from full to half of the maximum Vdd. However, it is possible to construct designs th...
 
Power Minimization using Simultaneous Gate Sizing, Dual-Vdd and Dual-Vth Assignment
Found in: Design Automation Conference
By Ashish Srivastava, Dennis Sylvester, David Blaauw
Issue Date:June 2004
pp. 783-787
We develop an approach to minimize total power in a dual-Vdd and dual-Vth design. The algorithm runs in two distinct phases. The first phase relies on upsizing to create slack and maximize low Vdd assignments in a backward topological manner. The second ph...
 
Tradeoffs between Gate Oxide Leakage and Delay for Dual T{ox} Circuits
Found in: Design Automation Conference
By Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar
Issue Date:June 2004
pp. 761-766
Gate oxide tunneling current (I{gate}) will become the dominant component of leakage in CMOS circuits as the physical oxide thickness (T{ox}) goes below 15?. Increasing the value of T{ox} reduces the leakage at the expense of an increase in delay, and a pr...
 
Concurrent Sizing, Vdd and V<sub>th</sub> Assignment for Low-Power Design
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Ashish Srivastava, Dennis Sylvester, David Blaauw
Issue Date:February 2004
pp. 10718
We present a sensitivity based algorithm for total power including dynamic and subthreshold leakage power minimization using simultaneous sizing, Vdd and Vth assignment. The proposed algorithm is implemented and tested on a set of combinational benchmark c...
   
A Simplified Transmission-Line Based Crosstalk Noise Model for On-Chip RLC Wiring
Found in: Asia and South Pacific Design Automation Conference
By Kanak Agarwal, Dennis Sylvester, David Blaauw
Issue Date:January 2004
pp. 858-864
In this paper, we present a new RLC crosstalk noise model that combines simplicity, accuracy, and generality. The new model is based on transmission line theory and is applicable to asymmetric driver and line configurations. The results show that the model...
 
Optimal Inductance for On-chip RLC Interconnections
Found in: Computer Design, International Conference on
By Shidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester
Issue Date:October 2003
pp. 264
We propose the concept of an optimal inductance value that can substantially reduce delay of global RLC signals while maintaining good signal integrity (low ringing/overshoot). We exploit the fact that inductance results in faster transition times to impro...
 
An Effective Capacitance Based Driver Output Model for On-Chip RLC Interconnects
Found in: Design Automation Conference
By Kanak Agarwal, Dennis Sylvester, David Blaauw
Issue Date:June 2003
pp. 376
This paper presents a new library compatible approach to gate-level timing characterization in the presence of RLC interconnect loads. We describe a two-ramp model based on transmission line theory that accurately predicts both the 50% delay and waveform s...
 
Simple Metrics for Slew Rate of RC Circuits Based on Two Circuit Moments
Found in: Design Automation Conference
By Kanak Agarwal, Dennis Sylvester, David Blaauw
Issue Date:June 2003
pp. 950
In this paper we introduce simple metrics for the slew rate of an RC circuit based on the first two circuit moments. We develop two new slew metrics, S2M (slew with 2 moments) and scaled S2M, that provide high accuracy with the advantage of simple closed f...
 
An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Robert Bai, Sarvesh Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David Blaauw
Issue Date:February 2003
pp. 149
With the explosion of portable electronic devices, power efficient processors have become increasingly important. In this paper we present a set of circuit techniques to implement a 32-bit low-power ARM processor, found commonly in embedded systems, using ...
 
Transition Aware Global Signaling (TAGS)
Found in: Quality Electronic Design, International Symposium on
By Himanshu Kaul, Dennis Sylvester
Issue Date:March 2002
pp. 53
We propose a new receiver to reduce the number of repeaters used in global wiring. The receiver stores the next state of the line while quiet. Upon detection of a transition at the end of the line the output is temporarily driven by the stored next state. ...
 
Future Performance Challenges in Nanometer Design
Found in: Design Automation Conference
By Himanshu Kaul, Dennis Sylvester
Issue Date:June 2001
pp. 3-8
We highlight several fundamental challenges to designing high-performance integrated circuits in nanometer-scale technologies (i.e. drawn feature sizes < 100 nm). Dynamic power scaling trends lead to major packaging problems. To alleviate these concerns...
 
Rethinking Deep-Submicron Circuit Design
Found in: Computer
By Dennis Sylvester, Kurt Keutzer
Issue Date:November 1999
pp. 25-33
<p>Several independent sources forecast that in deep-submicron (DSM) process geometries, 80 percent or more of the delays of critical paths will be directly linked to interconnect. This forecast is supported by the significant timing-closure problems...
 
Limits of Parallelism and Boosting in Dim Silicon
Found in: IEEE Micro
By Nathaniel Pinckney,Ronald G. Dreslinski,Korey Sewell,David Fick,Trevor Mudge,Dennis Sylvester,David Blaauw
Issue Date:September 2013
pp. 30-37
Supply-voltage scaling has stagnated in recent technology nodes, leading to so-called dark silicon. To increase overall chip multiprocessor (CMP) performance, it is necessary to improve the energy efficiency of individual tasks so that more tasks can be ex...
 
Centip3De: A 64-Core, 3D Stacked Near-Threshold System
Found in: IEEE Micro
By Ronald G. Dreslinski,David Fick,Bharan Giridhar,Gyouho Kim,Sangwon Seo,Matthew Fojtik,Sudhir Satpathy,Yoonmyung Lee,Daeyeon Kim,Nurrachman Liu,Michael Wieckowski,Gregory Chen,Dennis Sylvester,David Blaauw,Trevor Mudge
Issue Date:March 2013
pp. 8-16
Centip3De uses the synergy between 3D integration and near-threshold computing to create a reconfigurable system that provides both energy-efficient operation and techniques to address single-thread performance bottlenecks. The original Centip3De design is...
 
Sensor-Driven Reliability and Wearout Management
Found in: IEEE Design and Test of Computers
By Prashant Singh, Cheng Zhuo, Eric Karl, David Blaauw, Dennis Sylvester
Issue Date:September 2009
pp. 40-49
<p>Editor's note:</p><p>Gate oxide degradation is a key limiter to semiconductor reliability. Because of variations in gate oxide thickness, however, product reliability is often guaranteed by designing for the worst case. This article de...
 
Low power circuit design based on heterojunction tunneling transistors (HETTs)
Found in: Low Power Electronics and Design, International Symposium on
By Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, Dennis Sylvester, David Blaauw
Issue Date:August 2009
pp. 219-224
The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low supply voltages. This paper investigates extremely-low power circuits based o...
 
On the decreasing significance of large standard cells in technology mapping
Found in: Computer-Aided Design, International Conference on
By Jae-sun Seo, Igor L. Markov, Dennis Sylvester, David Blaauw
Issue Date:November 2008
pp. 116-121
Technology scaling reduces gate delays while wire delays may increase. Our work studies the interaction of this phenomenon with technology mapping and its impact on modern EDA flows. In particular, we demonstrate that the use of larger standard cells incre...
 
Optimal technology selection for minimizing energy and variability in low voltage applications
Found in: Low Power Electronics and Design, International Symposium on
By Mingoo Seok, Dennis Sylvester, David Blaauw
Issue Date:August 2008
pp. 9-14
Ultra Low voltage operation has recently drawn significant attention due to its large potential energy savings. However, typical design practices used for super-threshold operation are not necessarily compatible with the low voltage regime. Here, radically...
 
A robust edge encoding technique for energy-efficient multi-cycle interconnect
Found in: Low Power Electronics and Design, International Symposium on
By Jae-sun Seo, Dennis Sylvester, David Blaauw, Himanshu Kaul, Ram Krishnamurthy
Issue Date:August 2007
pp. 68-73
In this paper, we propose a new edge encoding technique to reduce the energy consumption in multi-cycle interconnects. Both average and worst-case energy are reduced by desynchronizing the edges of rising and falling transitions. In a 1.2V 65nm CMOS techno...
 
Self-Time Regenerators for High-Speed and Low-Power Interconnect
Found in: Quality Electronic Design, International Symposium on
By Jae-sun Seo, Prashant Singh, Dennis Sylvester, David Blaauw
Issue Date:March 2007
pp. 621-626
In this paper, we propose a new circuit technique called self-timed regenerator (STR) to improve both speed and power for on-chip global interconnects. The proposed circuits are placed along global wires to compensate the loss in resistive wires and to amp...
 
Modeling and Analysis of Parametric Yield under Power and Performance Constraints
Found in: IEEE Design and Test of Computers
By Rajeev R. Rao, David Blaauw, Dennis Sylvester, Anirudh Devgan
Issue Date:July 2005
pp. 376-385
Leakage current is a stringent constraint in today's ASIC designs. Effective parametric yield prediction must consider leakage current's dependence on chip frequency. The authors propose an analytical expression that includes both subthreshold and gate lea...
 
Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate
Found in: Quality Electronic Design, International Symposium on
By Harmander Singh Deogun, Dennis Sylvester, David Blaauw
Issue Date:March 2005
pp. 175-180
Neutron-induced single-event upsets have become increasingly problematic in aggressively scaled process technologies due to smaller nodal capacitances and reduced operating voltages. We present a probability-based analysis of neutron strikes on combination...
 
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization
Found in: Quality Electronic Design, International Symposium on
By Rahul Rao, Kanak Agarwal, Anirudh Devgan, Kevin Nowka, Dennis Sylvester, Richard Brown
Issue Date:March 2005
pp. 284-290
Parametric yield loss has become a serious concern in leakage dominated technologies. In this paper, we discuss the impact of leakage on parametric yield and show that leakage can cause yield window to shrink by imposing a two-sided constraint on the windo...
 
Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization
Found in: Quality Electronic Design, International Symposium on
By Harmander Singh Deogun, Rahul Rao, Dennis Sylvester, Richard Brown, Kevin Nowka
Issue Date:March 2005
pp. 88-93
Increased buffer insertion along on-chip global lines and the increasing contribution of leakage power have resulted in buffer leakage emerging as one of the chief contributors to system leakage power. In this paper, we present a novel power-gating scheme ...
 
DVS for On-Chip Bus Designs Based on Timing Error Correction
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor Mudge, Todd Austin
Issue Date:March 2005
pp. 80-85
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching pattern. This can result in significant performance slack at more typical operating...
 
Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits
Found in: Computer Design, International Conference on
By Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar
Issue Date:October 2004
pp. 228-233
Gate oxide tunneling current (I{gate}) is emerging as a key roadblock for device scaling in nanometer-scale CMOS circuits. A practical means to reduce I{gate} is to leverage dual T{ox} processes where non-critical transistors are assigned a thicker T{ox}. ...
 
A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters
Found in: Computer Design, International Conference on
By Saumil Shah, Kanak Agarwal, Dennis Sylvester
Issue Date:October 2004
pp. 138-143
High performance digital circuits require long bus lines to operate at very high frequencies, necessitating a large number of repeaters to be inserted along these lines. Power consumed by repeaters, particularly that contributed by subthreshold leakage, is...
 
Spatial Encoding Circuit Techniques for Peak Power Reduction of On-Chip High-Performance Buses
Found in: Low Power Electronics and Design, International Symposium on
By Himanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy
Issue Date:August 2004
pp. 194-199
We propose various low-latency spatial encoder circuits based on bus-invert coding for reducing peak energy and current in on-chip buses with minimum penalty on total latency. The encoders are implemented in dual-rail domino logic with interfaces for stati...
 
Variational Delay Metrics for Interconnect Timing Analysis
Found in: Design Automation Conference
By Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani Nassif, Sarma Vrudhula
Issue Date:June 2004
pp. 381-384
In this paper we develop an approach to model interconnect delay under process variability for timing analysis and physical design optimization. The technique allows for closed-form computation of interconnect delay probability density functions (PDFs) giv...
 
Leakage-and Crosstalk-Aware Bus Encoding for Total Power Reduction
Found in: Design Automation Conference
By Harmander S. Deogun, Rajeev R. Rao, Dennis Sylvester, David Blaauw
Issue Date:June 2004
pp. 779-782
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC delays. In this paper, we propose a new bus encoding algorithm and circuit sche...
 
Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Dongwoo Lee, Harmander Deogun, David Blaauw, Dennis Sylvester
Issue Date:February 2004
pp. 10494
Standby leakage current minimization is a pressing concern for mobile applications that rely on standby modes to extend battery life. Also, gate oxide leakage current (I<sub>gate</sub>) has become comparable to subthreshold leakage (I<sub>...
 
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