Search For:

Displaying 1-49 out of 49 total
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Greg Semeraro, Grigorios Magklis, Michael L. Scott
Issue Date:September 2002
pp. 141
Energy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be realized for adaptive storage structures such as caches, issue queues, and register files by disabling unnecessary storage resources. Prior studies ha...
 
Adaptive Cache Memories for SMT Processors
Found in: Digital Systems Design, Euromicro Symposium on
By Sonia Lopez, Oscar Garnica, David H. Albonesi, Steven Dropsho, Juan Lanchares, Jose I. Hidalgo
Issue Date:September 2010
pp. 331-338
Resizable caches can trade-off capacity for access speed to dynamically match the needs of the workload. In Simultaneous Multi-Threaded (SMT) cores, the caching needs can vary greatly across the number of threads and their characteristics, offering opportu...
 
Dynamically Trading Frequency for Complexity in a GALS Microprocessor
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Steven Dropsho, Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott
Issue Date:December 2004
pp. 157-168
Microprocessors are traditionally designed to provide
 
On-Chip Optical Technology in Future Bus-Based Multicore Designs
Found in: IEEE Micro
By Nevin Kırman, Meyrem Kırman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi
Issue Date:January 2007
pp. 56-66
This work investigates the integration of CMOS-compatible optical technology to on-chip coherent buses for future CMPs. The analysis results in a hierarchical optoelectrical bus that exploits the advantages of optical technology while abiding by projected ...
 
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, Jose F. Martinez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi
Issue Date:December 2006
pp. 492-503
Although silicon optical technology is still in its formative stages, and the more near-term application is chip-to-chip communication, rapid advances have been made in the development of on-chip optical interconnects. In this paper, we investigate the int...
 
The Energy Impact of Aggressive Loop Fusion
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By YongKang Zhu, Grigorios Magklis, Michael L. Scott, Chen Ding, David H. Albonesi
Issue Date:October 2004
pp. 153-164
Loop fusion combines corresponding iterations of different loops. It is traditionally used to decrease program run time, by reducing loop overhead and increasing data locality. In this paper, however, we consider its effect on energy.<div></div>...
 
Energy Efficient Co-Adaptive Instruction Fetch and Issue
Found in: Computer Architecture, International Symposium on
By Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose
Issue Date:June 2003
pp. 147
Front-end instruction delivery accounts for a significant fraction of the energy consumed in a dynamic superscalar processor. The issue queue in these processors serves two crucial roles: it bridges the front and back ends of the processor and serves as th...
 
Changes Ahead
Found in: IEEE Micro
By David H. Albonesi
Issue Date:September 2008
pp. 4
IEEE Micro's editor in chief describes changes planned for the magazine in the coming year. These include additions to the editorial and advisory boards, a shift in the selection criteria for the Top Picks issue to include long-term impact, and the develop...
 
Productive and Healthy Debate
Found in: IEEE Micro
By David H. Albonesi
Issue Date:November 2007
pp. 6
A productive, healthy debate is informative and insightful, and collectively moves the debaters and the audience closer to a potential solution or agreement by examining the issues from multiple viewpoints and critiquing those arguments. <em>Micro<...
 
Mixing It Up
Found in: IEEE Micro
By David H. Albonesi
Issue Date:July 2007
pp. 3-4
Micro's editor in chief introduces the topics covered by the four articles in this general-interest issue: an interconnection network using highly integrated photonic technology; the ManySim simulation framework for future large-scale chip-multiprocessors;...
 
Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences
Found in: IEEE Micro
By David H. Albonesi
Issue Date:November 2004
pp. 8-9
No summary available.
 
Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Sonia Lopez, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares
Issue Date:September 2007
pp. 416
Resizable caches can tradeoff capacity for access speed to dynamically match the needs of the workload. In single-threaded cores, resizable caches adapt to the phases of the running application. In Simultaneous Multi- Threaded (SMT) cores the caching needs...
   
Profile-based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor
Found in: Computer Architecture, International Symposium on
By Grigorios Magklis, Michael L. Scott, Greg Semeraro, David H. Albonesi, Steven Dropsho
Issue Date:June 2003
pp. 14
A Multiple Clock Domain (MCD) processor addresses the challenges of clock distribution and power dissipation by dividing a chip into several (coarse-grained) clock domains, allowing frequency and voltage to be reduced in domains that are not currently on t...
 
Future Directions in Computer Architecture Research
Found in: IEEE Micro
By David H. Albonesi
Issue Date:May 2010
pp. 5
<p>A year ago, the 36th International Symposium on Computer Architecture featured the latest installment of the Computer Architecture Research Directions workshop. CARD is a series of minipanels, in which two experts take somewhat opposing viewpoints...
 
Runtime Reconfiguration Techniques for Efficient General-Purpose Computation
Found in: IEEE Design and Test of Computers
By Bingxiong Xu, David H. Albonesi
Issue Date:January 2000
pp. 42-52
<p>By exploiting hardware partitioning and applying runtime reconfiguration techniques, microprocessor efficiency is significantly improved while retaining high clock speed, dense functionality, and conventional development tools.</p>
 
Managing Static Leakage Energy in Microprocessor Functional Units
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Steven Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman
Issue Date:November 2002
pp. 321
Static energy due to subthreshold leakage current is projected to become a major component of the total energy in high performance microprocessors. Many studies so far have examined and proposed techniques to reduce leakage in on-chip storage structures. I...
 
ReMAP: A Reconfigurable Architecture for Chip Multiprocessors
Found in: IEEE Micro
By Matthew A. Watkins, David H. Albonesi
Issue Date:January 2011
pp. 65-77
<p>ReMAP is a reconfigurable architecture for accelerating and parallelizing applications within a heterogeneous chip multiprocessor (CMP). Clusters of cores share a common reconfigurable fabric adaptable for individual thread computation or fine-gra...
 
ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Matthew A. Watkins, David H. Albonesi
Issue Date:December 2010
pp. 497-508
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common reconfigurable fabric that can be configured for individual thread computation ...
 
Moving Forward
Found in: IEEE Micro
By David H. Albonesi
Issue Date:November 2010
pp. 4-5
<p>Having reached the end of my second term as editor in chief, the time has come for Micro to move forward to the next phase of its evolution. I am delighted to announce that Dr. Erik Altman from IBM Research is the new Micro EIC. He has already beg...
 
Welcome A-Board
Found in: IEEE Micro
By David H. Albonesi
Issue Date:September 2009
pp. 2-5
<p>IEEE Micro Editor in Chief David H. Albonesi welcomes six new emmbers to teh IEEE Micro Editorial Board and previews this general interest issue.</p>
 
More Hot Stuff
Found in: IEEE Micro
By David H. Albonesi
Issue Date:May 2007
pp. 4-5
While leading computing corporations have instituted
 
Editor in Chief's Message: Truly
Found in: IEEE Micro
By David H. Albonesi
Issue Date:March 2007
pp. 4-5
Despite the move away from very high-frequency, high-ILP cores to multiple, more modest cores (
 
Standing on Solid Ground
Found in: IEEE Micro
By David H. Albonesi
Issue Date:January 2007
pp. 5-6
The new Editor in Chief of IEEE Micro introduces himself and the first issue of 2007. He thanks outgoing Editor in Chief Pradip Bose for his outstanding work on Micro during his tenure. He assesses the current state of the microarchitecture field, speculat...
 
Power-Efficient Error Tolerance in Chip Multiprocessors
Found in: IEEE Micro
By M. Wasiur Rashid, Edwin J. Tan, Michael C. Huang, David H. Albonesi
Issue Date:November 2005
pp. 60-70
As device dimensions continue to be scaled, microprocessors are becoming increasingly vulnerable to environmental disturbances such as a cosmic particle strike, which can cause transient errors. Thus, redundancy becomes more imperative to prevent operation...
 
Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By M. Wasiur Rashid, Edwin J. Tan, Michael C. Huang, David H. Albonesi
Issue Date:September 2005
pp. 315-328
<p>As device dimensions continue to be aggressively scaled, microprocessors are becoming increasingly vulnerable to the impact of undesired energy, such as that of a cosmic particle strike, which can cause transient errors. To prevent operational fai...
 
Mitigating Inductive Noise in SMT Processors
Found in: Low Power Electronics and Design, International Symposium on
By Wael El-Essawy, David H. Albonesi
Issue Date:August 2004
pp. 332-337
Simultaneous Multi-Threading, although effective in increasing processor throughput, exacerbates the inductive noise problem such that more expensive electronic solutions are required even with the use of previously proposed microarchitectural approaches. ...
 
Dynamically Tuning Processor Resources with Adaptive Processing
Found in: Computer
By David H. Albonesi, Rajeev Balasubramonian, Steven G. Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley E. Schuster
Issue Date:December 2003
pp. 49-58
<p>The <em>adaptive processing approach</em> improves microprocessor energy efficiency by dynamically tuning major resources during execution to better match varying application needs. This tuning usually involves reducing a resource's si...
 
Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor
Found in: IEEE Micro
By Grigorios Magklis, Greg Semeraro, David H. Albonesi, Steven G. Dropsho, Sandhya Dwarkadas, Michael L. Scott
Issue Date:November 2003
pp. 62-68
<p>Multiple clock domains is one solution to the increasing problem of propagating the clock signal across increasingly larger and faster chips. The ability to independently scale frequency and voltage in each domain creates a powerful means of reduc...
 
A Dynamically Tunable Memory Hierarchy
Found in: IEEE Transactions on Computers
By Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
Issue Date:October 2003
pp. 1243-1258
<p><b>Abstract</b>—The widespread use of repeaters in long wires creates the possibility of dynamically sizing regular on-chip structures. We present a tunable cache and translation lookaside buffer (TLB) hierarchy that leverages repeater...
 
Guest Editors' Introduction: Power and Complexity Aware Design
Found in: IEEE Micro
By Pradip Bose, David H. Albonesi, Diana Marculescu
Issue Date:September 2003
pp. 8-11
No summary available.
 
Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors
Found in: Computer Architecture, International Symposium on
By Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
Issue Date:June 2003
pp. 275
Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-delay-constrained process technologies. As increasing transistor counts allow ...
 
Dynamic Data Dependence Tracking and its Application to Branch Prediction
Found in: High-Performance Computer Architecture, International Symposium on
By Lei Chen, Steve Dropsho, David H. Albonesi
Issue Date:February 2003
pp. 65
<p>To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundamental limit to improving ILP is data dependences among instructions. If...
 
Front-End Policies for Improved Issue Efficiency in SMT Processors
Found in: High-Performance Computer Architecture, International Symposium on
By Ali El-Moursy, David H. Albonesi
Issue Date:February 2003
pp. 31
<p>The performance and power optimization of dynamic superscalar microprocessors requires striking a careful balance between exploiting parallelism and hardware simplification. Hardware structures which are needlessly complex may exacerbate critical ...
 
Dynamically Allocating Processor Resources between Nearby and Distant ILP
Found in: Computer Architecture, International Symposium on
By Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
Issue Date:July 2001
pp. 0026
Abstract: Modern superscalar processors use wide instruction issue widths and out-of-order execution in order to increase instruction-level parallelism (ILP). Because instructions must be committed in order so as to guarantee precise exceptions, increasing...
 
Selective Cache Ways: On-Demand Cache Resource Allocation
Found in: Microarchitecture, IEEE/ACM International Symposium on
By David H. Albonesi
Issue Date:November 1999
pp. 248
Increasing levels of microprocessor power dissipation call for new approaches at the architectural level that save energy by better matching of on-chip resources to application requirements. Selective cache ways provides the ability to disable a subset of ...
 
Improving the Memory Bandwidth of Highly-Integrated, Wide-Issue, Microprocessor-Based Systems
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By David H. Albonesi, Israel Koren
Issue Date:November 1997
pp. 126
Next generation, wide-issue processors will require greater memory bandwidth than provided by present memory hierarchy designs. We propose techniques for increasing the memory bandwidth of multi-ported L1 Dcaches, large on-chip L2 caches, and dedicated mem...
 
Reducing the Complexity of the Register File in Dynamic Superscalar Processors
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
Issue Date:December 2001
pp. 037
Dynamic superscalar processors execute multiple instructions out-of-order by looking for independent operations within a large window. The number of physical registers within the processor has a direct impact on the size of this window as most in-flight in...
 
Hiding Synchronization Delays in a GALS Processor Microarchitecture
Found in: Asynchronous Circuits and Systems, International Symposium on
By Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott, Steven G. Dropsho, Sandhya Dwarkadas
Issue Date:April 2004
pp. 159-169
We analyze an Alpha 21264-like Globally-Asynchronous, Locally-Synchronous (GALS) processor organized as a Multiple Clock Domain (MCD) microarchitecture and identify the architectural features of the processor that influence the limited performance degradat...
 
Flicker: a dynamically adaptive architecture for power limited multicore systems
Found in: Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA '13)
By Adam M. Izraelevitz, Christine A. Shoemaker, David H. Albonesi, Paula Petrica
Issue Date:June 2013
pp. 13-23
Future microprocessors may become so power constrained that not all transistors will be able to be powered on at once. These systems will be required to nimbly adapt to changes in the chip power that is allocated to general-purpose cores and to specialized...
     
Energy-aware meeting scheduling algorithms for smart buildings
Found in: Proceedings of the Fourth ACM Workshop on Embedded Sensing Systems for Energy-Efficiency in Buildings (BuildSys '12)
By Abhinandan Majumdar, David H. Albonesi, Pradip Bose
Issue Date:November 2012
pp. 161-168
The increasing worldwide concern over the energy consumption of commercial buildings calls for new approaches that analyze scheduled occupant activities and proactively take steps to curb building energy use. As one step in this direction, we propose to au...
     
A low-latency, high-throughput on-chip optical router architecture for future chip multiprocessors
Found in: ACM Journal on Emerging Technologies in Computing Systems (JETC)
By David H. Albonesi, Mark J. Cianchetti
Issue Date:June 2011
pp. 1-20
Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable chip performance within a given power envelope. While CMOS-compatible nanophot...
     
Dynamically managed multithreaded reconfigurable architectures for chip multiprocessors
Found in: Proceedings of the 19th international conference on Parallel architectures and compilation techniques (PACT '10)
By David H. Albonesi, Matthew A. Watkins
Issue Date:September 2010
pp. 41-52
Prior work has demonstrated that reconfigurable logic can significantly benefit certain applications. However, reconfigurable architectures have traditionally suffered from high area overhead and limited application coverage. We present a dynamically manag...
     
Scalable thread scheduling and global power management for heterogeneous many-core architectures
Found in: Proceedings of the 19th international conference on Parallel architectures and compilation techniques (PACT '10)
By Christine A. Shoemaker, David H. Albonesi, Jonathan A. Winter
Issue Date:September 2010
pp. 29-40
Future many-core microprocessors are likely to be heterogeneous, by design or due to variability and defects. The latter type of heterogeneity is especially challenging due to its unpredictability. To minimize the performance and power impact of these hard...
     
Phastlane: a rapid transit optical routing network
Found in: Proceedings of the 36th annual international symposium on Computer architecture (ISCA '09)
By David H. Albonesi, Joseph C. Kerekes, Mark J. Cianchetti
Issue Date:June 2009
pp. 70-73
Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable chip performance within a given power envelope. While CMOS-compatible nanophot...
     
Addressing thermal nonuniformity in SMT workloads
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By David H. Albonesi, Jonathan A. Winter, Jonathan A. Winter
Issue Date:May 2008
pp. 1-28
We explore DTM techniques within the context of uniform and nonuniform SMT workloads. While DVS is suitable for addressing workloads with uniformly high temperatures, for nonuniform workloads, performance loss occurs because of the slowdown of the cooler t...
     
Synergistic temperature and energy management in GALS processor architectures
Found in: Proceedings of the 2006 international symposium on Low power electronics and design (ISLPED '06)
By David H. Albonesi, YongKang Zhu
Issue Date:October 2006
pp. 55-60
We propose a synergistic temperature and energy management scheme for GALS processors. Localized DVS is applied in domains that contain hotspots, permitting other critical domains to run unabated, thereby reducing performance cost relative to global DVS, a...
     
A microarchitectural-level step-power analysis tool
Found in: Proceedings of the 2002 international symposium on Low power electronics and design (ISLPED '02)
By Balaram Sinharoy, David H. Albonesi, Wael El-Essawy
Issue Date:August 2002
pp. 263-266
Clock gating is an effective means for reducing average power consumption. However, clock gating can exacerbate maximum cycle-to-cycle current swings, or the step-power (Ldi/dt) problem. We present a microarchitecture-level step-power simulator and demonst...
     
Tradeoffs in power-efficient issue queue design
Found in: Proceedings of the 2002 international symposium on Low power electronics and design (ISLPED '02)
By Alper Buyuktosunoglu, David H. Albonesi, Peter W. Cook, Pradip Bose, Stanley E. Schuster
Issue Date:August 2002
pp. 184-189
A major consumer of microprocessor power is the issue queue. Several microprocessors, including the Alpha 21264 and POWER4TM, use a compacting latch-based issue queue design which has the advantage of simplicity of design and verification. The disadvantage...
     
Dynamically allocating processor resources between nearby and distant ILP
Found in: Proceedings of the 28th annual international symposium on Computer architecture (ISCA '01)
By David H. Albonesi, Rajeev Balasubramonian, Sandhya Dwarkadas
Issue Date:June 2001
pp. 125-131
Modern superscalar processors use wide instruction issue widths and out-of-order execution in order to increase instruction-level parallelism (ILP). Because instructions must be committed in order so as to guarantee precise exceptions, increasing ILP impli...
     
 1