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Displaying 1-50 out of 61 total
Guest Editors' Introduction: Top Picks from the Computer Architecture Conferences of 2007
Found in: IEEE Micro
By Sarita Adve, David Brooks, Craig Zilles
Issue Date:January 2008
pp. 8-11
This special issue represents the fifth anniversary of <em>IEEE Micro</em>'s Top Picks from the Computer Architecture Conferences. A program committee of 33 highly respected architects from industry and academia selected 10 of 70 submissions fo...
 
CPUs, GPUs, and Hybrid Computing
Found in: IEEE Micro
By David Brooks
Issue Date:September 2011
pp. 4-6
This introduction to the special issue discusses advances and challenges in the field of hybrid CPU/GPU computing.
 
Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
Found in: IEEE Micro
By Xiaoyao Liang, Gu-Yeon Wei, David Brooks
Issue Date:January 2009
pp. 127-138
<p>Process variations will significantly degrade the performance benefits of future microprocessors as they move toward nanoscale technology. Device parameter fluctuations can introduce large variations in peak operation among chips, cores on a singl...
 
Applied inference: Case studies in microarchitectural design
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By Benjamin C. Lee, David Brooks, David Brooks
Issue Date:September 2010
pp. 1-37
We propose and apply a new simulation paradigm for microarchitectural design evaluation and optimization. This paradigm enables more comprehensive design studies by combining spatial sampling and statistical inference. Specifically, this paradigm (i) defin...
     
Helix: Making the Extraction of Thread-Level Parallelism Mainstream
Found in: IEEE Micro
By Simone Campanoni,Timothy M. Jones,Glenn Holloway,Gu-Yeon Wei,David Brooks
Issue Date:July 2012
pp. 8-18
Improving system performance increasingly depends on exploiting microprocessor parallelism, yet mainstream compilers still don&amp;#x0027;t parallelize code automatically. Helix automatically parallelizes general-purpose programs without requiring any ...
 
Implementing a hybrid SRAM / eDRAM NUCA architecture
Found in: High-Performance Computing, International Conference on
By Javier Lira,Carlos Molina,David Brooks,Antonio Gonzalez
Issue Date:December 2011
pp. 1-10
Advances in technology allowed for integrating DRAM-like structures into the chip, called embedded DRAM (eDRAM). This technology has already been successfully implemented in some GPUs and other graphic-intensive SoC, like game consoles. The most recent pro...
 
Achieving uniform performance and maximizing throughput in the presence of heterogeneity
Found in: High-Performance Computer Architecture, International Symposium on
By Krishna K. Rangan, Michael D. Powell, Gu-Yeon Wei, David Brooks
Issue Date:February 2011
pp. 3-14
Continued scaling of process technologies is critical to sustaining improvements in processor frequencies and performance. However, shrinking process technologies exacerbates process variations -- the deviation of process parameters from their target speci...
 
Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David Brooks
Issue Date:December 2010
pp. 77-88
Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel Core2 Duo processor. By sensing on-die ...
 
Voltage Noise in Production Processors
Found in: IEEE Micro
By Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David Brooks
Issue Date:January 2011
pp. 20-28
<p>Voltage variations are a major challenge in processor design. Here, researchers characterize the voltage noise characteristics of programs as they run to completion on a production Core 2 Duo processor. Furthermore, they characterize the implicati...
 
The Accelerator Store framework for high-performance, low-power accelerator-based systems
Found in: IEEE Computer Architecture Letters
By Michael J. Lyons, Mark Hempstead, Gu-Yeon Wei, David Brooks
Issue Date:July 2010
pp. 53-56
Hardware acceleration can increase performance and reduce energy consumption. To maximize these benefits, accelerator- based systems that emphasize computation on accelerators (rather than on general purpose cores) should be used. We introduce the &#82...
 
Can Subthreshold and Near-Threshold Circuits Go Mainstream?
Found in: IEEE Micro
By Benton H. Calhoun, David Brooks
Issue Date:July 2010
pp. 80-85
<p>Editors' Note: Recent research has shown the potential benefits of subthreshold or near-threshold operation, which gives up a substantial degree of speed in order to reduce energy per operation. This is an excellent trade-off for many tasks, such ...
 
Predicting Voltage Droops Using Recurring Program and Microarchitectural Event Activity
Found in: IEEE Micro
By Vijay Janapa Reddi, Meeta Gupta, Glenn Holloway, Michael D. Smith, Gu-Yeon Wei, David Brooks
Issue Date:January 2010
pp. 110-110
<p>Shrinking feature size and diminishing supply voltage are making circuits more sensitive to supply voltage fluctuations within a microprocessor. If left unattended, voltage fluctuations can lead to timing violations or even transistor lifetime iss...
 
The design of a bloom filter hardware accelerator for ultra low power systems
Found in: Low Power Electronics and Design, International Symposium on
By Michael J. Lyons, David Brooks
Issue Date:August 2009
pp. 371-376
Battery-powered embedded systems require low energy usage to extend system lifetime. These systems must power many components for long periods of time and are particularly sensitive to energy use. Recent techniques for reducing energy consumption in wirele...
 
Place and route considerations for voltage interpolated designs
Found in: Quality Electronic Design, International Symposium on
By Kevin Brownell, Ali Durlov Khan, David Brooks, Gu-Yeon Wei
Issue Date:March 2009
pp. 594-600
Voltage interpolation is a promising post fabrication technique for combating the effects of process variations. The benefits of voltage interpolation are well understood. Its implementation in a VLSI-CAD flow has been considered through the synthesis stag...
 
CPR: Composable performance regression for scalable multiprocessor models
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Benjamin C. Lee, Jamison Collins, Hong Wang, David Brooks
Issue Date:November 2008
pp. 270-281
Uniprocessor simulators track resource utilization cycle by cycle to estimate performance. Multiprocessor simulators, however, must account for synchronization events that increase the cost of every cycle simulated and shared resource contention that incre...
 
Evaluation of voltage interpolation to address process variations
Found in: Computer-Aided Design, International Conference on
By Kevin Brownell, Gu-Yeon Wei, David Brooks
Issue Date:November 2008
pp. 529-536
Post-fabrication tuning provides a promising design approach to mitigate the performance and power overheads of process variation in advanced fabrication technologies. This paper explores design considerations and VLSI-CAD support for a recently proposed p...
 
Instruction-driven clock scheduling with glitch mitigation
Found in: Low Power Electronics and Design, International Symposium on
By Gu-Yeon Wei, David Brooks, Ali Durlov Khan, Xiaoyao Liang
Issue Date:August 2008
pp. 357-362
Instruction-driven clock scheduling is a mechanism that minimizes clock power in deeply-pipelined datapaths. Analysis of realistic processor workloads shows a preponderance of bubbles persist through pipelines like the floating point unit. Clock scheduling...
 
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
Found in: Computer Architecture, International Symposium on
By Xiaoyao Liang, Gu-Yeon Wei, David Brooks
Issue Date:June 2008
pp. 191-202
Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introduce large variations in peak operation among chips, among cores on a single chip...
 
Process Variation Tolerant 3T1D-Based Cache Architectures
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks
Issue Date:December 2007
pp. 15-26
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM (6-transistor static memory) structures and will become critical with continu...
 
Towards a software approach to mitigate voltage emergencies
Found in: Low Power Electronics and Design, International Symposium on
By Meeta Sharma Gupta, Krishna K. Rangan, Michael D. Smith, Gu-Yeon Wei, David Brooks
Issue Date:August 2007
pp. 123-128
Increases in peak current draw and reductions in the operating voltages ofprocessors continue to amplify the importance of dealing with voltage fluctuations in processors. One approach suggested has been to not only react to these fluctuations but also att...
 
Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors
Found in: IEEE Micro
By David Brooks, Robert P. Dick, Russ Joseph, Li Shang
Issue Date:May 2007
pp. 49-62
Power is the source of the greatest problems facing microprocessor designers. Rapid power variation brings transient errors. High power densities bring high temperatures, harming reliability and increasing leakage power. The wages of power are bulky, short...
 
System-on-Chip Architecture Design for Intelligent Sensor Networks
Found in: Intelligent Information Hiding and Multimedia Signal Processing, International Conference on
By Wai-Chi Fang, Sharon Kedar, Susan Owen, Gu-Yeon Wei, David Brooks, Jonathan Lees
Issue Date:December 2006
pp. 579-582
While wireless sensor networks can generically be used for a wide variety of applications, breakthrough innovations are most often achieved when driven by a genuine need or application, with its specific system-level and science-related requirements and ob...
 
Mitigating the Impact of Process Variations on Processor Register Files and Execution Units
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Xiaoyao Liang, David Brooks
Issue Date:December 2006
pp. 504-514
Design variability due to die-to-die and within-die process variations has the potential to significantly reduce the maximum operating frequency and the effective yield of high-performance microprocessors in future process technology generations. One serio...
 
Dynamic-Compiler-Driven Control for Microprocessor Energy and Performance
Found in: IEEE Micro
By Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David Brooks
Issue Date:January 2006
pp. 119-129
A general dynamic-compilation environment offers power and performance control opportunities for microprocessors. The authors propose a dynamic-compiler-driven runtime voltage and frequency optimizer. A prototype of their design, implemented and deployed i...
 
A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Qiang Wu, Margaret Martonosi, Douglas W. Clark, V.J. Reddi, Dan Connors, Youfeng Wu, Jin Lee, David Brooks
Issue Date:November 2005
pp. 271-282
<p>Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardware, OS timeinterrupts, or static-compiler techniques. However, subs...
 
An Ultra Low Power System Architecture for Sensor Network Applications
Found in: Computer Architecture, International Symposium on
By Mark Hempstead, Nikhil Tripathi, Patrick Mauro, Gu-Yeon Wei, David Brooks
Issue Date:June 2005
pp. 208-219
Recent years have seen a burgeoning interest in embedded wireless sensor networks with applications ranging from habitat monitoring to medical applications. Wireless sensor networks have several important attributes that require special attention to device...
 
Performance, Energy, and Thermal Considerations for SMT and CMP Architectures
Found in: High-Performance Computer Architecture, International Symposium on
By Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadron
Issue Date:February 2005
pp. 71-82
Simultaneous multithreading (SMT) and chip multi-processing (CMP) both allow a chip to achieve greater throughput, but their relative energy-efficiency and thermal properties are still poorly understood. This paper uses Turandot, PowerTimer, and HotSpot to...
 
TinyBench: The Case For A Standardized Benchmark Suite for TinyOS Based Wireless Sensor Network Devices
Found in: Local Computer Networks, Annual IEEE Conference on
By Mark Hempstead, Matt Welsh, David Brooks
Issue Date:November 2004
pp. 585-586
The growing wireless sensor network research community lacks a standard method for evaluating hardware platforms. Traditional benchmark suites do not sufficiently address the needs of sensor network designers. This work provides motivation for a benchmark ...
   
Evaluating Techniques for Exploiting Instruction Slack
Found in: Computer Design, International Conference on
By Yau Chin, John Sheu, David Brooks
Issue Date:October 2004
pp. 375-378
In many workloads, 25% to 50% of instructions have slack allowing them to be delayed without impacting performance. To exploit this slack, processors may implement more power-efficient, longer latency pipelines or provide dynamically scaled pipelines using...
 
Integrated Analysis of Power and Performance for Pipelined Microprocessors
Found in: IEEE Transactions on Computers
By Victor Zyuban, David Brooks, Viji Srinivasan, Michael Gschwind, Pradip Bose, Philip N. Strenski, Philip G. Emma
Issue Date:August 2004
pp. 1004-1016
<p><b>Abstract</b>—Choosing the pipeline depth of a microprocessor is one of the most critical design decisions that an architect must make in the concept phase of a microprocessor design. To be successful in today's cost/performance mark...
 
Understanding the Energy Efficiency of Simultaneous Multithreading
Found in: Low Power Electronics and Design, International Symposium on
By Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadron, Pradip Bose
Issue Date:August 2004
pp. 44-49
Simultaneous multithreading (SMT) has proven to be an effective method of increasing the performance of microprocessors by extracting additional instruction-level parallelism from multiple threads. In current microprocessor designs, power-efficiency is of ...
 
Eliminating Voltage Emergencies via Microarchitectural Voltage Control Feedback and Dynamic Optimization
Found in: Low Power Electronics and Design, International Symposium on
By Kim Hazelwood, David Brooks
Issue Date:August 2004
pp. 326-331
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations that stress the power-delivery network. Recent research has focused on hardware-o...
 
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
Found in: High-Performance Computer Architecture, International Symposium on
By Russ Joseph, David Brooks, Margaret Martonosi
Issue Date:February 2003
pp. 79
<p>Increasing focus on power dissipation issues in current microprocessors has led to a host of proposals for clock gating and other power-saving techniques. While generally effective at reducing average power, many of these techniques have the undes...
 
Optimizing Pipelines for Power and Performance
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor Zyuban, Philip N. Strenski, Philip G. Emma
Issue Date:November 2002
pp. 333
During the concept phase and definition of next generation high-end processors, power and performance will need to be weighted appropriately to deliver competitive cost/performance. It is not enough to adopt a CPI-centric view alone in early-stage definiti...
 
Dynamic Thermal Management for High-Performance Microprocessors
Found in: High-Performance Computer Architecture, International Symposium on
By David Brooks, Margaret Martonosi
Issue Date:January 2001
pp. 0171
Abstract: With the increasing clock rate and transistor count of today's microprocessors, power dissipation is becoming a critical component of system design complexity. Thermal and power-delivery issues are becoming especially critical for high-performanc...
 
Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance
Found in: High-Performance Computer Architecture, International Symposium on
By David Brooks, Margaret Martonosi
Issue Date:January 1999
pp. 13
In general-purpose microprocessors, recent trends have pushed towards 64-bit word widths, primarily to accommodate the large addressing needs of some programs. Many integer problems, however, rarely need the full 64-bit dynamic range these CPUs provide. In...
 
Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures
Found in: 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)
By Yakun Sophia Shao,Brandon Reagen,Gu-Yeon Wei,David Brooks
Issue Date:June 2014
pp. 97-108
Hardware specialization, in the form of accelerators that provide custom datapath and control for specific algorithms and applications, promises impressive performance and energy advantages compared to traditional architectures. Current research in acceler...
   
HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs
Found in: 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)
By Simone Campanoni,Kevin Brownell,Svilen Kanev,Timothy M. Jones,Gu-Yeon Wei,David Brooks
Issue Date:June 2014
pp. 217-228
Data dependences in sequential programs limit parallelization because extracted threads cannot run independently. Although thread-level speculation can avoid the need for precise dependence analysis, communication overheads required to synchronize actual d...
   
ISA-independent workload characterization and its implications for specialized architectures
Found in: 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
By Yakun Sophia Shao,David Brooks
Issue Date:April 2013
pp. 245-255
Specialized architectures will become increasingly important as the computing industry demands more energy-efficient designs. The application-centric design style for these architectures is heavily dependent on workload characterization of intrinsic progra...
   
A circuit level implementation of an adaptive issue queue for power-aware microprocessors
Found in: Proceedings of the 11th Great Lakes Symposium on VLSI (GLSVLSI '01)
By Alper Buyuktosunoglu, David Albonesi, David Brooks, Peter Cook, Pradip Bose, Stanley Schuster
Issue Date:March 2001
pp. 73-78
The concept of a “transparent repeater1,” which is an amplifier circuit designed to minimize the delay introduced by highly resistive interconnect lines in high speed digital circuits, is introduced and described in this paper. An insertion met...
     
Wattch: A Framework for Architectural-Level Power Analysis and Optimizations
Found in: Computer Architecture, International Symposium on
By Margaret Martonosi, Vivek Tiwari, David Brooks
Issue Date:June 2000
pp. 83
Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most ex...
 
Evaluation of voltage stacking for near-threshold multicore computing
Found in: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design (ISLPED '12)
By David Brooks, Gu-Yeon Wei, Sae Kyu Lee
Issue Date:July 2012
pp. 373-378
This paper evaluates voltage stacking in the context of near-threshold multicore computing. Key attributes of voltage stacking are investigated using results from a test-chip prototype built in 150nm FDSOI CMOS. By "stacking" logic blocks on top of each ot...
     
XIOSim: power-performance modeling of mobile x86 cores
Found in: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design (ISLPED '12)
By David Brooks, Gu-Yeon Wei, Svilen Kanev
Issue Date:July 2012
pp. 267-272
Simulation is one of the main vehicles of computer architecture research. In this paper, we present XIOSim - a highly detailed microarchitectural simulator targeted at mobile x86 microprocessors. The simulator execution model that we propose is a blend bet...
     
The accelerator store: A shared memory framework for accelerator-based systems
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By David Brooks, Mark Hempstead, Gu-Yeon Wei, Michael J. Lyons
Issue Date:January 2012
pp. 1-22
This paper presents the many-accelerator architecture, a design approach combining the scalability of homogeneous multi-core architectures and system-on-chip's high performance and power-efficient hardware accelerators. In preparation for systems containin...
     
Eliminating voltage emergencies via software-guided code transformations
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By David Brooks, Gu-Yeon Wei, Gu-Yeon Wei, Kim Hazelwood, Kim Hazelwood, Meeta S. Gupta, Meeta S. Gupta, Michael D. Smith, Michael D. Smith, Simone Campanoni, Simone Campanoni, Vijay Janapa Reddi, Vijay Janapa Reddi
Issue Date:September 2010
pp. 1-28
In recent years, circuit reliability in modern high-performance processors has become increasingly important. Shrinking feature sizes and diminishing supply voltages have made circuits more sensitive to microprocessor supply voltage fluctuations. These flu...
     
Tribeca: design for PVT variations with local recovery and fine-grained adaptation
Found in: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (Micro-42)
By David Brooks, Gu-Yeon Wei, Jude A. Rivers, Meeta S. Gupta, Pradip Bose
Issue Date:December 2009
pp. 435-446
With continued advances in CMOS technology, parameter variations are emerging as a major design challenge. Irregularities during the fabrication of a microprocessor and variations of voltage and temperature during its operation widen worst-case timing marg...
     
An accelerator-based wireless sensor network processor in 130nm CMOS
Found in: Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems (CASES '09)
By David Brooks, Gu-Yeon Wei, Mark Hempstead
Issue Date:October 2009
pp. 215-222
Networks of ultra-low-power nodes capable of sensing, computation, and wireless communication have applications in medicine, science, industrial automation, and security. Over the past few years, deployments of wireless sensor networks (WSNs) have utilized...
     
The design of a bloom filter hardware accelerator for ultra low power systems
Found in: Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design (ISLPED '09)
By David Brooks, Michael J. Lyons
Issue Date:August 2009
pp. 1-2
Battery-powered embedded systems require low energy usage to extend system lifetime. These systems must power many components for long periods of time and are particularly sensitive to energy use. Recent techniques for reducing energy consumption in wirele...
     
Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack
Found in: Proceedings of the 46th Annual Design Automation Conference (DAC '09)
By David Brooks, Gu-yeon Wei, Meeta S. Gupta, Michael D. Smith, Simone Campanoni, Vijay Janapa Reddi
Issue Date:July 2009
pp. 788-793
Power constrained designs are becoming increasingly sensitive to supply voltage noise. We propose a hardware-software collaborative approach to enable aggressive operating margins: a checkpoint-recovery mechanism corrects margin violations, while a run-tim...
     
Thread motion: fine-grained power management for multi-core systems
Found in: Proceedings of the 36th annual international symposium on Computer architecture (ISCA '09)
By David Brooks, Gu-Yeon Wei, Krishna K. Rangan
Issue Date:June 2009
pp. 70-73
Dynamic voltage and frequency scaling (DVFS) is a commonly-used power-management scheme that dynamically adjusts power and performance to the time-varying needs of running programs. Unfortunately, conventional DVFS, relying on off-chip regulators, faces li...
     
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