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Displaying 1-50 out of 165 total
Limits of Parallelism and Boosting in Dim Silicon
Found in: IEEE Micro
By Nathaniel Pinckney,Ronald G. Dreslinski,Korey Sewell,David Fick,Trevor Mudge,Dennis Sylvester,David Blaauw
Issue Date:September 2013
pp. 30-37
Supply-voltage scaling has stagnated in recent technology nodes, leading to so-called dark silicon. To increase overall chip multiprocessor (CMP) performance, it is necessary to improve the energy efficiency of individual tasks so that more tasks can be ex...
 
Centip3De: A 64-Core, 3D Stacked Near-Threshold System
Found in: IEEE Micro
By Ronald G. Dreslinski,David Fick,Bharan Giridhar,Gyouho Kim,Sangwon Seo,Matthew Fojtik,Sudhir Satpathy,Yoonmyung Lee,Daeyeon Kim,Nurrachman Liu,Michael Wieckowski,Gregory Chen,Dennis Sylvester,David Blaauw,Trevor Mudge
Issue Date:March 2013
pp. 8-16
Centip3De uses the synergy between 3D integration and near-threshold computing to create a reconfigurable system that provides both energy-efficient operation and techniques to address single-thread performance bottlenecks. The original Centip3De design is...
 
Design and Analysis of Power Distribution Networks in PowerPC Microprocessors
Found in: Design Automation Conference
By Rajendran Panda, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden, David Blaauw, Abhijit Dharchoudhury
Issue Date:June 1998
pp. 738-743
We present a methodology for the design and analysis of power grids in the PowerPC™ microprocessors. The methodology covers the need for power grid analysis across all stages of the design process. A case study showing the application of this methodology t...
 
Impact of Low-Impedance Substrate on Power Supply Integrity
Found in: IEEE Design and Test of Computers
By Rajendran Panda, Savithri Sundareswaran, David Blaauw
Issue Date:May 2003
pp. 16-22
<p><em>Editor?s note:</em><div>Although it is tempting to think of the power grid as an independent medium of the transfer of energy from the package to the devices in the IC, some second-order technology-related effects can sometim...
 
Scaling towards kilo-core processors with asymmetric high-radix topologies
Found in: 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)
By Nilmini Abeyratne,Reetuparna Das,Qingkun Li,Korey Sewell,Bharan Giridhar,Ronald G. Dreslinski,David Blaauw,Trevor Mudge
Issue Date:February 2013
pp. 496-507
In this paper, we explore the challenges in scaling on-chip networks towards kilo-core processors. Current low-radix topologies optimize for fast local communication, but do not scale well to kilo-core systems because of the large number of routers require...
 
Sensor-Driven Reliability and Wearout Management
Found in: IEEE Design and Test of Computers
By Prashant Singh, Cheng Zhuo, Eric Karl, David Blaauw, Dennis Sylvester
Issue Date:September 2009
pp. 40-49
<p>Editor's note:</p><p>Gate oxide degradation is a key limiter to semiconductor reliability. Because of variations in gate oxide thickness, however, product reliability is often guaranteed by designing for the worst case. This article de...
 
Low power circuit design based on heterojunction tunneling transistors (HETTs)
Found in: Low Power Electronics and Design, International Symposium on
By Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, Dennis Sylvester, David Blaauw
Issue Date:August 2009
pp. 219-224
The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low supply voltages. This paper investigates extremely-low power circuits based o...
 
Reconfigurable energy efficient near threshold cache architectures
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Ronald G. Dreslinski, Gregory K. Chen, Trevor Mudge, David Blaauw, Dennis Sylvester, Krisztian Flautner
Issue Date:November 2008
pp. 459-470
Battery life is an important concern for modern embedded processors. Supply voltage scaling techniques can provide an order of magnitude reduction in energy. Current commercial memory technologies have been limited in the degree of supply voltage scaling t...
 
On the decreasing significance of large standard cells in technology mapping
Found in: Computer-Aided Design, International Conference on
By Jae-sun Seo, Igor L. Markov, Dennis Sylvester, David Blaauw
Issue Date:November 2008
pp. 116-121
Technology scaling reduces gate delays while wire delays may increase. Our work studies the interaction of this phenomenon with technology mapping and its impact on modern EDA flows. In particular, we demonstrate that the use of larger standard cells incre...
 
A statistical approach for full-chip gate-oxide reliability analysis
Found in: Computer-Aided Design, International Conference on
By Kaviraj Chopra, Cheng Zhuo, David Blaauw, Dennis Sylvester
Issue Date:November 2008
pp. 698-705
Gate oxide breakdown is a key factor limiting the useful lifetime of an integrated circuit. Unfortunately, the conventional approach for full chip oxide reliability analysis assumes a uniform oxide-thickness for all devices. In practice, however, gate-oxid...
 
STEEL: A technique for stress-enhanced standard cell library design
Found in: Computer-Aided Design, International Conference on
By Brian T. Cline, Vivek Joshi, Dennis Sylvester, David Blaauw
Issue Date:November 2008
pp. 691-697
Mobility degradation and device scaling limitations have led process engineers to develop new techniques that introduce mechanical stress in MOSFET channels, which results in enhanced carrier transport. New fabrication steps strive to increase carrier mobi...
 
Variation-aware gate sizing and clustering for post-silicon optimized circuits
Found in: Low Power Electronics and Design, International Symposium on
By Cheng Zhuo, David Blaauw, Dennis Sylvester
Issue Date:August 2008
pp. 105-110
As technology is aggressively scaled, nano-regime VLSI designs are becoming increasingly susceptible to process variations. Unlike pre-silicon optimization, post-silicon techniques can tune the individual die to better meet the power-delay constraints. Thi...
 
Optimal technology selection for minimizing energy and variability in low voltage applications
Found in: Low Power Electronics and Design, International Symposium on
By Mingoo Seok, Dennis Sylvester, David Blaauw
Issue Date:August 2008
pp. 9-14
Ultra Low voltage operation has recently drawn significant attention due to its large potential energy savings. However, typical design practices used for super-threshold operation are not necessarily compatible with the low voltage regime. Here, radically...
 
Transistor-Specific Delay Modeling for SSTA
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Brian Cline, Kaviraj Chopra, David Blaauw, Andres Torres, Savithri Sundareswaran
Issue Date:March 2008
pp. 592-597
SSTA has received a considerable amount of attention in recent years. However, it is a general rule that any approach can only be as accurate as the underlying models. Thus, variation models are an important research topic, in addition to the development o...
 
Fast and Accurate Waveform Analysis with Current Source Models
Found in: Quality Electronic Design, International Symposium on
By Vineeth Veetil, Dennis Sylvester, David Blaauw
Issue Date:March 2008
pp. 53-56
Recently current source models (CSMs) have become popular for use in standard cell characterization and static timing analysis. However, there has not been any detailed study of what aspects of the gate behavior should be modeled for sufficient accuracy, a...
 
Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures
Found in: Quality Electronic Design, International Symposium on
By Eric Karl, Dennis Sylvester, David Blaauw
Issue Date:March 2008
pp. 391-395
Continued technology scaling exacerbates the incidence of degradation and failure in integrated circuits due to mechanisms such as oxide breakdown, negative bias temperature instability and electromigration. This work analyzes the impact of different facto...
 
An Energy Efficient Parallel Architecture Using Near Threshold Operation
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Ronald G. Dreslinkski, Bo Zhai, Trevor Mudge, David Blaauw, Dennis Sylvester
Issue Date:September 2007
pp. 175-188
Subthreshold circuit design, while energy efficient, has the drawback of performance degradation. To retain the excellent energy efficiency while reducing performance loss, we propose to investigate near subthreshold techniques on chip multiprocessors (CMP...
 
Energy efficient near-threshold chip multi-processing
Found in: Low Power Electronics and Design, International Symposium on
By Bo Zhai, Ronald G. Dreslinski, David Blaauw, Trevor Mudge, Dennis Sylvester
Issue Date:August 2007
pp. 32-37
Subthreshold circuit design has become a popular approach for building energy efficient digital circuits. One drawback is performance degradation due to the exponentially reduced driving current. This had limited subthreshold circuits to relatively low per...
 
A robust edge encoding technique for energy-efficient multi-cycle interconnect
Found in: Low Power Electronics and Design, International Symposium on
By Jae-sun Seo, Dennis Sylvester, David Blaauw, Himanshu Kaul, Ram Krishnamurthy
Issue Date:August 2007
pp. 68-73
In this paper, we propose a new edge encoding technique to reduce the energy consumption in multi-cycle interconnects. Both average and worst-case energy are reduced by desynchronizing the edges of rising and falling transitions. In a 1.2V 65nm CMOS techno...
 
Power Grid Physics and Implications for CAD
Found in: IEEE Design and Test of Computers
By Sanjay Pant, Eli Chiprout, David Blaauw
Issue Date:May 2007
pp. 246-254
An accurate analysis of supply noise in power distribution networks is essential to ensure reliable performance in high-performance designs. Recently, several analysis and optimization techniques for on-chip power grid networks have been proposed. However,...
 
Investigating Crosstalk in Sub-Threshold Circuits
Found in: Quality Electronic Design, International Symposium on
By Mini Nanua, David Blaauw
Issue Date:March 2007
pp. 639-646
Ultra-low power designs are increasingly exploiting the sub-threshold region of operation of CMOS circuits. In order to ensure correct functionality in a design, it is necessary to guarantee signal integrity. We evaluate crosstalk in an industrial micropro...
 
Self-Time Regenerators for High-Speed and Low-Power Interconnect
Found in: Quality Electronic Design, International Symposium on
By Jae-sun Seo, Prashant Singh, Dennis Sylvester, David Blaauw
Issue Date:March 2007
pp. 621-626
In this paper, we propose a new circuit technique called self-timed regenerator (STR) to improve both speed and power for on-chip global interconnects. The proposed circuits are placed along global wires to compensate the loss in resistive wires and to amp...
 
Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks
Found in: Asia and South Pacific Design Automation Conference
By Sanjay Pant, David Blaauw
Issue Date:January 2007
pp. 757-762
Power supply noise increases the circuit delay, which may lead to performance failure of a design. Decoupling capacitance (decap) addition is effective in reducing the power supply noise, thus making the supply network more robust in presence of large swit...
 
ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon
Found in: IEEE Design and Test of Computers
By Dennis Sylvester, David Blaauw, Eric Karl
Issue Date:November 2006
pp. 484-490
With continued technology scaling, silicon is becoming increasingly less predictable. Recent years have brought an acceleration of wear-out mechanisms, such as oxide breakdown and NBTI, which occur over a part's lifetime. Manufacturing device failure rates...
 
Logic SER Reduction through Flipflop Redesign
Found in: Quality Electronic Design, International Symposium on
By Vivek Joshi, Rajeev R. Rao, David Blaauw, Dennis Sylvester
Issue Date:March 2006
pp. 611-616
In this paper, we present a new flipflop sizing scheme that efficiently immunizes combinational logic circuits from the effects of radiation induced single event transients (SET). The proposed technique leverages the effect of temporal masking by selective...
 
Modeling and Analysis of Parametric Yield under Power and Performance Constraints
Found in: IEEE Design and Test of Computers
By Rajeev R. Rao, David Blaauw, Dennis Sylvester, Anirudh Devgan
Issue Date:July 2005
pp. 376-385
Leakage current is a stringent constraint in today's ASIC designs. Effective parametric yield prediction must consider leakage current's dependence on chip frequency. The authors propose an analytical expression that includes both subthreshold and gate lea...
 
Energy Optimization of Subthreshold-Voltage Sensor Network Processors
Found in: Computer Architecture, International Symposium on
By Leyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd Austin, David Blaauw
Issue Date:June 2005
pp. 197-207
Sensor network processors and their applications are a growing area of focus in computer system research and design. Inherent to this design space is a reduced processing performance requirement and extremely high energy constraints, such that sensor netwo...
 
Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate
Found in: Quality Electronic Design, International Symposium on
By Harmander Singh Deogun, Dennis Sylvester, David Blaauw
Issue Date:March 2005
pp. 175-180
Neutron-induced single-event upsets have become increasingly problematic in aggressively scaled process technologies due to smaller nodal capacitances and reduced operating voltages. We present a probability-based analysis of neutron strikes on combination...
 
Statistical Timing Based Optimization using Gate Sizing
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Aseem Agarwal, Kaviraj Chopra, David Blaauw
Issue Date:March 2005
pp. 400-405
The increased dominance of intra-die process variations has motivated the field of Statistical Static Timing Analysis (SSTA) and has raised the need for SSTA-based circuit optimization. In this paper, we propose a new sensitivity based, statistical gate si...
 
DVS for On-Chip Bus Designs Based on Timing Error Correction
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor Mudge, Todd Austin
Issue Date:March 2005
pp. 80-85
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching pattern. This can result in significant performance slack at more typical operating...
 
Leakage Current Modeling in PD SOI Circuits
Found in: Quality Electronic Design, International Symposium on
By Mini Nanua, David Blaauw, Chanhee Oh
Issue Date:March 2005
pp. 113-117
In this paper we demonstrate the transient behavior of off-state device leakage due to signal switching history in PD SOI devices. We address the leakage modeling for PD SOI circuits taking input switching history into account and demonstrate that the off-...
 
Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation
Found in: IEEE Micro
By Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd Austin, Trevor Mudge, Nam Sung Kim, Krisztián Flautner
Issue Date:November 2004
pp. 10-20
Dynamic voltage scaling is one of the more effective and widely used methods for power-aware computing. Here is a dvs approach that uses dynamic detection and correction of circuit timing errors to tune processor supply voltage and eliminate the need for v...
 
Single-VDD and Single-VT Super-Drowsy Techniques for Low-Leakage High-Performance Instruction Caches
Found in: Low Power Electronics and Design, International Symposium on
By Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor Mudge
Issue Date:August 2004
pp. 54-57
In this paper, we present a circuit technique that supports a super-drowsy mode with a single-VDD. In addition, we perform a detailed working set analysis for various cache line update policies for placing lines in a drowsy state. The analysis presents a p...
 
Reducing Pipeline Energy Demands with Local DVS and Dynamic Retiming
Found in: Low Power Electronics and Design, International Symposium on
By Seokwoo Lee, Shidhartha Das, Toan Pham, Todd Austin, David Blaauw, Trevor Mudge
Issue Date:August 2004
pp. 319-324
The quadratic relationship between voltage and energy has made dynamic voltage scaling (DVS) one of the most powerful techniques to reduce system power demands. Recently, techniques such as Razor DVS, voltage overscaling, and Intelligent Energy Management ...
 
Statistical Optimization of Leakage Power Considering Process Variations using Dual-Vth and Sizing
Found in: Design Automation Conference
By Ashish Srivastava, Dennis Sylvester, David Blaauw
Issue Date:June 2004
pp. 773-778
Increasing levels of process variability in sub-100nm CMOS design has become a critical concern for performance and power constraint designs. In this paper, we propose a new statistically aware Dual-Vt and sizing optimization that considers both the variab...
 
Variational Delay Metrics for Interconnect Timing Analysis
Found in: Design Automation Conference
By Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani Nassif, Sarma Vrudhula
Issue Date:June 2004
pp. 381-384
In this paper we develop an approach to model interconnect delay under process variability for timing analysis and physical design optimization. The technique allows for closed-form computation of interconnect delay probability density functions (PDFs) giv...
 
A Stochastic Approach To Power Grid Analysis
Found in: Design Automation Conference
By Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
Issue Date:June 2004
pp. 171-176
Power supply integrity analysis is critical in modern high performance designs. In this paper, we propose a stochastic approach to obtain statistical information about the collective IR and LdI/dt drop in a power supply network. The currents drawn from the...
 
Parametric Yield Estimation Considering Leakage Variability
Found in: Design Automation Conference
By Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester
Issue Date:June 2004
pp. 442-447
Leakage current has become a stringent constraint in modern processor designs in addition to traditional constraints on frequency. Since leakage current exhibits a strong inverse correlation with circuit delay, effective parametric yield prediction must co...
 
Leakage-and Crosstalk-Aware Bus Encoding for Total Power Reduction
Found in: Design Automation Conference
By Harmander S. Deogun, Rajeev R. Rao, Dennis Sylvester, David Blaauw
Issue Date:June 2004
pp. 779-782
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC delays. In this paper, we propose a new bus encoding algorithm and circuit sche...
 
Theoretical and Practical Limits of Dynamic Voltage Scaling
Found in: Design Automation Conference
By Bo Zhai, David Blaauw, Dennis Sylvester, Krisztian Flautner
Issue Date:June 2004
pp. 868-873
Dynamic voltage scaling (DVS) is a popular approach for energy reduction of integrated circuits. Current processors that use DVS typically have an operating voltage range from full to half of the maximum Vdd. However, it is possible to construct designs th...
 
Static Timing Analysis using Backward Signal Propagation
Found in: Design Automation Conference
By Dongwoo Lee, Vladimir Zolotov, David Blaauw
Issue Date:June 2004
pp. 664-669
In this paper, we address the problem of signal pruning in static timing analysis (STA). Traditionally, signals are propagated through the circuit and are pruned, such that only the signal with the latest arrival time at each node is propagated forward. Th...
 
Power Minimization using Simultaneous Gate Sizing, Dual-Vdd and Dual-Vth Assignment
Found in: Design Automation Conference
By Ashish Srivastava, Dennis Sylvester, David Blaauw
Issue Date:June 2004
pp. 783-787
We develop an approach to minimize total power in a dual-Vdd and dual-Vth design. The algorithm runs in two distinct phases. The first phase relies on upsizing to create slack and maximize low Vdd assignments in a backward topological manner. The second ph...
 
Circuit-Aware Architectural Simulation
Found in: Design Automation Conference
By Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd Austin, David Blaauw, Trevor Mudge
Issue Date:June 2004
pp. 305-310
Architectural simulation has achieved a prominent role in the system design cycle by providing designers the ability to quickly examine a wide variety of design choices. however, the recent trend in system design toward architectures that react to circuit-...
 
Statistical Gate Delay Model Considering Multiple Input Switching
Found in: Design Automation Conference
By Aseem Agarwal, Florentin Dartu, David Blaauw
Issue Date:June 2004
pp. 658-663
There is an increased dominance of intra-die process variations, creating a need for an accurate and fast statistical timing analysis. Most of the recent proposed approaches assume a Single Input Switching model. Our experiments show that SIS underestimate...
 
Mobile Supercomputers
Found in: Computer
By Todd Austin, David Blaauw, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, Wayne Wolf
Issue Date:May 2004
pp. 81-83
Current trends in computer architecture and power cannot meet the demands of mobile supercomputing. Significant innovation is required.
 
Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids
Found in: Quality Electronic Design, International Symposium on
By Woo Hyung Lee, Sanjay Pant, David Blaauw
Issue Date:March 2004
pp. 131-136
Power supply integrity has become a critical concern in modern chip design. To date, analysis of so-called LdI/dt drop in supply networks has mostly focused inductance of the package, which is the predominant factor in inductive voltage drop. However, with...
 
Making Typical Silicon Matter with Razor
Found in: Computer
By Todd Austin, David Blaauw, Trevor Mudge, Krisztián Flautner
Issue Date:March 2004
pp. 57-65
<p>Voltage scaling has emerged as a powerful technology for addressing the power challenges that current on-chip densities pose. Razor is a voltage-scaling technology based on dynamic, in-situ detection and correction of circuit-timing errors. Razor ...
 
Concurrent Sizing, Vdd and V<sub>th</sub> Assignment for Low-Power Design
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Ashish Srivastava, Dennis Sylvester, David Blaauw
Issue Date:February 2004
pp. 10718
We present a sensitivity based algorithm for total power including dynamic and subthreshold leakage power minimization using simultaneous sizing, Vdd and Vth assignment. The proposed algorithm is implemented and tested on a set of combinational benchmark c...
   
Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Dongwoo Lee, Harmander Deogun, David Blaauw, Dennis Sylvester
Issue Date:February 2004
pp. 10494
Standby leakage current minimization is a pressing concern for mobile applications that rely on standby modes to extend battery life. Also, gate oxide leakage current (I<sub>gate</sub>) has become comparable to subthreshold leakage (I<sub>...
 
A Simplified Transmission-Line Based Crosstalk Noise Model for On-Chip RLC Wiring
Found in: Asia and South Pacific Design Automation Conference
By Kanak Agarwal, Dennis Sylvester, David Blaauw
Issue Date:January 2004
pp. 858-864
In this paper, we present a new RLC crosstalk noise model that combines simplicity, accuracy, and generality. The new model is based on transmission line theory and is applicable to asymmetric driver and line configurations. The results show that the model...
 
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