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Displaying 1-9 out of 9 total
RIIF - Reliability information interchange format
Found in: 2012 IEEE 18th International On-Line Testing Symposium (IOLTS 2012)
By Adrian Evans,Michael Nicolaidis,Shi-Jie Wen,Dan Alexandrescu,Enrico Costenaro
Issue Date:June 2012
pp. 103-108
In this paper, a new standard language called RIIF (Reliability Information Interchange Format) is defined which enables designers to specify the failure characteristics and reliability requirements for simple and complex components. This language enables ...
 
A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance
Found in: 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)
By Shrikanth Ganapathy,Ramon Canal,Dan Alexandrescu,Enrico Costenaro,Antonio Gonzalez,Antonio Rubio
Issue Date:September 2012
pp. 472-477
In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variati...
 
A real-case application of a synergetic design-flow-oriented SER analysis
Found in: 2012 IEEE 18th International On-Line Testing Symposium (IOLTS 2012)
By Miguel Vilchis,Ramnath Venkatraman,Enrico Costenaro,Dan Alexandrescu
Issue Date:June 2012
pp. 43-48
We present a methodology that investigates SEEs in complex SOCs. The analysis integrates tightly with the design flow and provides static and dynamic de-rating algorithms. This approach is in good agreement with alpha testing results obtained from a 40nm C...
 
Towards optimized functional evaluation of SEE-induced failures in complex designs
Found in: 2012 IEEE 18th International On-Line Testing Symposium (IOLTS 2012)
By Dan Alexandrescu,Enrico Costenaro
Issue Date:June 2012
pp. 182-187
Single Event Effects strongly impact the reliability of electronic circuits and systems, requiring careful SER characterization and adequately sized mitigation strategy. The SER study aims at providing relevant information about the circuit behavior in the...
 
A Practical Approach to Single Event Transients Analysis for Highly Complex Designs
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Dan Alexandrescu,Enrico Costenaro,Michael Nicolaidis
Issue Date:October 2011
pp. 155-163
Single Event Transients are considerably more difficult to model, simulate and analyze than the closely-related Single Event Upsets. The work environment may cause a myriad of distinctive transient pulses in various cell types that are used in widely diffe...
 
Highs and lows of radiation testing
Found in: On-Line Testing Symposium, IEEE International
By Dan Alexandrescu, Anne-Lise Lhomme-Perrot, Erwin Schaefer, Cyrille Beltrando
Issue Date:June 2009
pp. 179
The presentation concerns a practical approach for dealing with difficulties associated to real time testing in a natural environment of microelectronic devices.
 
A Systematical Method of Quantifying SEU FIT
Found in: On-Line Testing Symposium, IEEE International
By Shi-Jie Wen, Dan Alexandrescu, Renaud Perez
Issue Date:July 2008
pp. 109-114
We present a practical, systematical method for the evaluation of the Soft Error Rate (SER) of microelectronic devices. Existing methodologies, practices and tools are integrated in a common approach while highlighting the need for specific data or tools. ...
 
Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors
Found in: VLSI Test Symposium, IEEE
By Michael Nicolaidis, Renaud Perez, Dan Alexandrescu
Issue Date:May 2008
pp. 371-376
CMOS nanometric technologies are increasingly sensitive to soft errors, including SEUs affecting storage cells and SETs initiated in the combinational logic, and eventually captured by some latches or flip-flops. SEUs affecting latches or flip-flops are by...
 
New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis
Issue Date:November 2002
pp. 99
This work considers a SET (single event transient) fault simulation technique to evaluate the probability that a transient pulse, born in the combinational logic, may be latched in a storage cell. Fault injection procedures and a fast fault simulation algo...
 
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