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Displaying 1-10 out of 10 total
A Taylor Expansion Diagram Approach for Nano-CMOS RTL Leakage Optimization
Found in: Electronic System Design, International Symposium on
By S. Banerjee, J. Mathew, D. K. Pradhan, S. P. Mohanty, M. Ciesielski
Issue Date:December 2010
pp. 71-76
Due to exponential behavior of gate-oxide leakage current with temperature and technology scaling, leakage power plays important role in nano − CMOS circuit. In this paper, we present simultaneous scheduling and binding algorithm for optimizing leakage cur...
A fast error correction technique for matrix multiplication algorithms
Found in: On-Line Testing Symposium, IEEE International
By C. Argyrides, C. A. L. Lisboa, D. K. Pradhan, L. Carro
Issue Date:June 2009
pp. 133-137
Temporal redundancy techniques will no longer be able to cope with radiation induced soft errors in technologies beyond the 45 nm node, because transients will last longer than the cycle time of circuits. The use of spatial redundancy techniques will also ...
Improving reliability for bit parallel finite field multipliers using Decimal Hamming
Found in: IEEE East-West Design & Test Symposium (EWDTS 2010)
By N Mavrogiannakis,C Argyrides,D K Pradhan
Issue Date:September 2010
pp. 69-72
Technology evolution dictates ever increasing density of transistors in chips, lower power consumption and higher performance. In such environment occurrence of multiple-bit upsets (MBUs) is a concern. That, together with the presence of fault-related atta...
Single Event Upset Detection and Correction
Found in: Information Technology, International Conference on
By Jawar Singh, J. Mathew, M. Hosseinabady, D. K. Pradhan
Issue Date:December 2007
pp. 13-18
This paper proposes a low cost solution to detect and correct a transient faults in registers of a design. The proposed method realizes a single- event upset detection and correction (SEU-DC) technique. The detection and correction of SEU in registers of a...
Multiple Bit Error Detection and Correction in GF Arithmetic Circuits
Found in: Electronic System Design, International Symposium on
By J. Mathew, S. Banerjee, P. Mahesh, D. K. Pradhan, A. M. Jabir, S. P. Mohanty
Issue Date:December 2010
pp. 101-106
This paper presents a design technique for multiple bit error correctable (fault tolerant) polynomial basis (PB) multipliers over GF(2^m). These multipliers are the building blocks in certain types of cryptographic hardware, e.g. the Elliptic Curve Crypto ...
Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m)
Found in: VLSI Design, International Conference on
By H. Rahaman, J. Mathew, D. K. Pradhan
Issue Date:January 2007
pp. 479-484
In this paper, a C-testable implementation of polynomial basis (PB) bit parallel (BP) multiplier over the Galois fields of form GF(2m) for detecting stuck-at faults in multiplier circuits has been proposed. The length of the constant test set is only 8. Th...
Improving Performance of TCP over Wireless Networks
Found in: Distributed Computing Systems, International Conference on
By Bikram S. Bakshi, P. Krishna, N. H. Vaidya, D. K. Pradhan
Issue Date:May 1997
pp. 365
Transmission Control Protocol~(TCP) assumes a relatively reliable underlying network where most packet losses are due to congestion. In a wireless network, however, packet losses will occur more often due to unreliable wireless links than due to congestion...
C-testable S-box implementation for secure advanced encryption standard
Found in: On-Line Testing Symposium, IEEE International
By H. Rahaman, J. Mathew, A. Jabir, D. K. Pradhan
Issue Date:June 2009
pp. 210-211
We propose a C-testable S-box implementation which is one of the most complex blocks in AES hardware implementation. Only 12 constant vectors are sufficient to achieve 100% fault coverage in the S-box. C-testability is achieved with an extra hardware overh...
Reliability aware yield improvement technique for nanotechnology based circuits
Found in: Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes (SBCCI '09)
By C. A. Lisboa, C. Argyrides, D. K. Pradhan, G. Dimosthenous, L. Carro
Issue Date:August 2009
pp. 1-6
Lithography based IC manufacturing is approaching its physical limits in terms of feature size. In this scenario, nanotechnology based manufacturing, relying on self-assembly of nanotubes or nanowires, has been predicted as an alternative to CMOS technolog...
A multiprocessor network suitable for single-chip VLSI implementation
Found in: Proceedings of the 11th annual international symposium on Computer architecture (ISCA '84)
By D. K. Pradhan, M. R. Samatham
Issue Date:January 1984
pp. 325-333
This paper presents a multiprocessor network architecture suitable for VLSI implementation. The proposed class of architectures is based on De Bruijn graphs which are distinct from the well-studied shuffle-exchange graphs. Compared to these latter De Bruij...