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Displaying 1-30 out of 30 total
SBST for on-line detection of hard faults in multiprocessor applications under energy constraints
Found in: On-Line Testing Symposium, IEEE International
By A. Merentitis, D. Margaris, N. Kranitis, A. Paschalis, D. Gizopoulos
Issue Date:July 2010
pp. 62-67
Software-Based Self-Test (SBST) has emerged as an effective method for on-line testing of processors integrated in non safety-critical systems. However, especially for multi-core processors, the notion of dependability encompasses not only high quality on-...
 
Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers
Found in: VLSI Test Symposium, IEEE
By M. Psarakis, A. Paschalis, N. Kranitis, D. Gizopoulos, Y. Zorian
Issue Date:April 2001
pp. 0015
The modified Booth array multiplier is the most ubiquitous multiplier architecture in the datapaths of either general purpose microprocessors or specialized Digital Signal Processors. Sequential fault testing for Booth array multipliers has never been prop...
 
Software-Based Self-Test for Pipelined Processors: A Case Study
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By M. Hatzimihail, M. Psarakis, G. Xenoulis, D. Gizopoulos, A. Paschalis
Issue Date:October 2005
pp. 535-543
<p>Software-Based Self-Test (SBST) for processors and processor-based systems recently captured the interest of test technology researchers and practitioners due to its several advantages over traditional hardware Built-In Self-Test (BIST). In this p...
 
Effective Low Power BIST for Datapaths
Found in: Design, Automation and Test in Europe Conference and Exhibition
By D. Gizopoulos, N. Kranitis, M. Psarakis, A. Paschalis, Y. Zorian
Issue Date:March 2000
pp. 757
Power in processing cores (microprocessors, DSPs) is primarily consumed in the datapath part. Among the datapath functional modules, multipliers consume the largest amount of power due to their size and complexity. We propose a low power BIST scheme for da...
 
Testing combinational iterative logic arrays for realistic faults
Found in: VLSI Test Symposium, IEEE
By D. Gizopoulos, D. Nikolos, A. Paschalis
Issue Date:May 1995
pp. 0035
Abstract: In this paper we give the fundamental theory for testing one or two-dimensional Iterative Logic Arrays (ILAs) with respect to realistic faults requiring two-pattern or generally n-pattern tests. We give conditions so that C-testability and linear...
 
Optimal Periodic Testing of Intermittent Faults In Embedded Pipelined Processor Applications
Found in: Design, Automation and Test in Europe Conference and Exhibition
By N. Kranitis, A. Merentitis, N. Laoutaris, G. Theodorou, A. Paschalis, D. Gizopoulos, C. Halatsis
Issue Date:March 2006
pp. 21
Today's nanometer technology trends have a very negative impact on the reliability of semiconductor products. Intermittent faults constitute the largest part of reliability failures that are manifested in the field during the semiconductor product operatio...
 
On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By G. Xenoulis, M. Psarakis, D. Gizopoulos, A. Paschalis
Issue Date:September 2007
pp. 379-397
On-line periodic testing of microprocessors is a viable low-cost alternative for a wide variety of embedded systems which cannot afford hardware or software redundancy techniques but necessitate the detection of intermittent or permanent faults. Low-cost, ...
 
Selecting Power-Optimal SBST Routines for On-Line Processor Testing
Found in: European Test Symposium, IEEE
By A. Merentitis, N. Kranitis, A. Paschalis, D. Gizopoulos
Issue Date:May 2007
pp. 111-116
Software-Based Self-Test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the most popular applications falling in this category are the various mobile devic...
 
Enhanced self-configurability and yield in multicore grids
Found in: On-Line Testing Symposium, IEEE International
By E. Kolonis, M. Nicolaidis, D. Gizopoulos, M. Psarakis, J.H. Collet, P. Zajac
Issue Date:June 2009
pp. 75-80
As we move deeper in the nanotechnology era, computer architecture is solicited to manipulate tremendous numbers of devices per chip with high defect densities. These trends provide new computing opportunities but efficiently exploiting them will require a...
 
An Input Vector Monitoring Concurrent BIST scheme exploiting
Found in: On-Line Testing Symposium, IEEE International
By I. Voyiatzis, D. Gizopoulos, A. Paschalis
Issue Date:June 2009
pp. 206-207
Input Vector Monitoring Concurrent Built-In Self Test schemes provide the capability to perform testing while the Circuit Under Test operates normally, by exploiting vectors that appear at the inputs of the CUT during its normal operation. The Concurrent T...
 
Functional Self-Testing for Bus-Based Symmetric Multiprocessors
Found in: Design, Automation and Test in Europe Conference and Exhibition
By A. Apostolakis, D. Gizopoulos, M. Psarakis, A. Paschalis
Issue Date:March 2008
pp. 1304-1309
Functional, instruction-based self-testing of microprocessors has recently emerged as an effective alternative or supplement to other testing approaches, and is progressively adopted by major microprocessor manufacturers. In this paper, we study, for first...
 
An asynchronous totally self-checking two-rail code error indicator
Found in: VLSI Test Symposium, IEEE
By N. Gaitanis, D. Gizopoulos, A. Paschalis, P. Kostarakis
Issue Date:May 1996
pp. 151
In this paper an asynchronous TSC two-rail code error indicator is presented. Such an error indicator memorises error indications {00,11} generated by TSC checkers with time duration greater than a tolerant limit T and can be used to detect not only faults...
 
Architectures for online error detection and recovery in multicore processors
Found in: 2011 Design, Automation & Test in Europe
By D Gizopoulos,M Psarakis,S V Adve,P Ramachandran,S K S Hari,D Sorin,A Meixner,A Biswas,X Vera
Issue Date:March 2011
pp. 1-6
The huge investment in the design and production of multicore processors may be put at risk because the emerging highly miniaturized but unreliable fabrication technologies will impose significant barriers to the life-long reliable operation of future chip...
   
A software-based self-test methodology for in-system testing of processor cache tag arrays
Found in: On-Line Testing Symposium, IEEE International
By G. Theodorou, N. Kranitis, A. Paschalis, D. Gizopoulos
Issue Date:July 2010
pp. 159-164
Software-Based Self-Test (SBST) has emerged as an effective alternative for processor manufacturing and in-system testing. For small memory arrays that lack BIST circuitry such as cache tag arrays, SBST can be a flexible and low-cost solution for March tes...
 
A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs
Found in: On-Line Testing Symposium, IEEE International
By P. Kenterlis, N. Kranitis, A. Paschalis, D. Gizopoulos, M. Psarakis
Issue Date:July 2006
pp. 235-241
In this paper, we introduce a fully automated low cost hardware/software platform for efficiently performing fault emulation experiments targeting SEUs in the configuration bits of FPGA devices, without the need for expensive radiation experiments. We prop...
 
Accumulator-Based Weighted Pattern Generation
Found in: On-Line Testing Symposium, IEEE International
By I. Voyiatzis, D. Gizopoulos, A. Paschalis
Issue Date:July 2005
pp. 215-220
<p>Weighted pseudorandom BIST schemes have been efficiently utilized in order to drive down the number of vectors required to achieve complete fault coverage in Built in Self Test (BIST) applications. Sets of patterns comprising weights 0, 0.5 and 1 ...
 
An effective BIST scheme for carry-save and carry-propagate array multipliers
Found in: Asian Test Symposium
By D. Gizopoulos, A. Paschalis, Y. Zorian
Issue Date:November 1995
pp. 298
Array multipliers, due to their high regularity, are efficiently designed as parts of complex VLSI devices. Such embedded multipliers have low controllability and observability, making the use of appropriate BIST schemes a necessity. This paper introduces ...
 
A Functional Self-Test Approach for Peripheral Cores in Processor-Based SoCs
Found in: On-Line Testing Symposium, IEEE International
By A. Apostolakis, M. Psarakis, D. Gizopoulos, A. Paschalis
Issue Date:July 2007
pp. 271-276
Functional Software-Based Self-Testing (SBST) of mi-croprocessors and processor-based testing of Systems-on-Chip (SoCs) have recently attracted the attention of test technology research community because they provide an effective alternative to other tradi...
 
A concurrent BIST scheme for on-line/off-line testing based on a pre-computed test set
Found in: Test Conference, International
By I. Voyiatzis, D. Gizopoulos, A. Paschalis, C. Halatsis
Issue Date:November 2005
pp. 8 pp.-1125
Manufacturing testing is carried-out once in order to ensure the correct operation of the circuit under test right after fabrication, while either periodic off-line testing or concurrent on-line testing is carried-out in order to ensure that the circuit un...
 
Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores
Found in: Test Conference, International
By N. Kranitis, G. Xenoulis, A. Paschalis, D. Gizopoulos, Y. Zorian
Issue Date:October 2003
pp. 431
Embedded processor testing techniques based on the execution of self-test routines, have been recently proposed as an effective alternative to classical hardware Built-In Self Test. Software-based self-testing provides at-speed testing capability and does ...
 
Low-Cost, On-Line Software-Based Self-Testing of Embedded Processor Cores
Found in: On-Line Testing Symposium, IEEE International
By G. Xenoulis, D. Gizopoulos, N. Kranitis, A. Paschalis
Issue Date:July 2003
pp. 149
A comprehensive online test strategy requires both concurrent and non-concurrent fault detection capabilities to guarantee SoCs?s successful normal operation in-field at any level of its life cycle. While concurrent fault detection is mainly achieved by ha...
 
Instruction-Based Self-Testing of Processor Cores
Found in: VLSI Test Symposium, IEEE
By N. Kranitis, A. Paschalis, D. Gizopoulos, Y. Zorian
Issue Date:May 2002
pp. 0223
Instruction-based self-testing of embedded processor cores provides an excellent technique for balancing the testing effort for complex Systems-on-Chip (SoC) between slow, inexpensive external testers and embedded code stored in memory cores. In this paper...
 
Effective Software Self-Test Methodology for Processor Cores
Found in: Design, Automation and Test in Europe Conference and Exhibition
By N. Kranitis, A. Paschalis, D. Gizopoulos, Y. Zorian
Issue Date:March 2002
pp. 0592
Software self-testing for embedded processor cores based on their instruction set, is a topic of increasing interest since it provides an excellent test resource partitioning technique for sharing the testing task of complex Systems-on-Chip (SoC) between s...
 
Deterministic Software-Based Self-Testing of Embedded Processor Cores
Found in: Design, Automation and Test in Europe Conference and Exhibition
By A. Paschalis, D. Gizopoulos, N. Kranitis, M. Psarakis, Y. Zorian
Issue Date:March 2001
pp. 0092
Abstract: A deterministic software-based self-testing methodology for processor cores is introduced that efficiently tests the processor datapath modules without any modification of the processor structure. It provides a guaranteed high fault coverage with...
 
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
Found in: Quality Electronic Design, International Symposium on
By N. Kranitis, M. Psarakis, D. Gizopoulos, A. Paschalis, Y. Zorian
Issue Date:March 2001
pp. 343
Effective Built-In Self-Test (BIST) schemes using deterministic sequences generated by small counters have been proposed in the past for the common multiplier/accumulator pair. In this paper we show how near complete testability can be achieved with a regu...
 
Low Power/Energy BIST Scheme for Datapaths
Found in: VLSI Test Symposium, IEEE
By D. Gizopoulos, N. Kranitis, M. Psarakis, A Paschalis, Y. Zorian
Issue Date:May 2000
pp. 23
Power in processing cores (microprocessors, DSPs) is primarily consumed in the functional modules of the datapath. Among these modules, multipliers consume the largest amount of power due to their size and complexity. We propose low power BIST schemes for ...
 
An Effective BIST Architecture for Fast Multiplier Cores
Found in: Design, Automation and Test in Europe Conference and Exhibition
By A. Paschalis, N. Kranitis, M. Psarakis, D. Gizopoulos, Y. Zorian
Issue Date:March 1999
pp. 117
Wallace tree summation in conjunction with Booth encoding are well known techniques to design fast multiplier cores widely used as embedded cores in the design of complex systems on chip. Testing of such multiplier cores deeply embedded in complex Ics requ...
 
Functional self-testing for bus-based symmetric multiprocessors
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '08)
By A. Apostolakis, A. Paschalis, D. Gizopoulos, M. Psarakis
Issue Date:March 2008
pp. 1-30
Functional, instruction-based self-testing of microprocessors has recently emerged as an effective alternative or supplement to other testing approaches, and is progressively adopted by major microprocessor manufacturers. In this paper, we study, for first...
     
Effective low power BIST for datapaths (poster paper)
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '00)
By A. Paschalis, D. Gizopoulos, M. Psarakis, N. Kranitis, Y. Zorian
Issue Date:March 2000
pp. 757
In this paper, we consider the new and evocative work on tangible interfaces and the issues this raises in the light of some old lessons of HCI. In doing so, we make the point that many of these lessons of good design still apply, even when we are consider...
     
An effective BIST architecture for fast multiplier cores
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '99)
By A. Paschalis, D. Gizopoulos, M. Psarakis, N. Kranitis, Y. Zorian
Issue Date:January 1999
pp. 28-es
In this paper, we consider the new and evocative work on tangible interfaces and the issues this raises in the light of some old lessons of HCI. In doing so, we make the point that many of these lessons of good design still apply, even when we are consider...
     
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