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Displaying 1-13 out of 13 total
A hybrid HW-SW approach for intermittent error mitigation in streaming-based embedded systems
Found in: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012)
By M. M. Sabry,D. Atienza,F. Catthoor
Issue Date:March 2012
pp. 1110-1113
Recent advances in process technology augment the systems-on-chip (SoCs) functionality per unit area with the substantial decrease of device features. However, features abatement triggers new reliability issues such as the single-event multi-bit upset (SMU...
 
Improving the Fault Tolerance of Nanometric PLA Designs
Found in: Design, Automation and Test in Europe Conference and Exhibition
By F. Angiolini, M.H.B. Jamaa, D. Atienza, L. Benini, G. De Micheli
Issue Date:April 2007
pp. 110
Several alternative building blocks have been proposed to replace planar transistors, among which a prominent spot belongs to nanometric filaments such as silicon nanowires (SiNWs) and carbon nanotubes (CNTs). However, chips leveraging these nanoscale stru...
 
Thermal balancing of liquid-cooled 3D-MPSoCs using channel modulation
Found in: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012)
By M. M. Sabry,A. Sridhar,D. Atienza
Issue Date:March 2012
pp. 599-604
While possessing the potential to replace conventional air-cooled heat sinks, inter-tier microchannel liquid cooling of 3D ICs also creates the problem of increased thermal gradients from the fluid inlet to outlet ports [1, 2]. These cooling-induced therma...
 
A real-time compressed sensing-based personal electrocardiogram monitoring system
Found in: 2011 Design, Automation & Test in Europe
By K Kanoun,H Mamaghanian,N Khaled,D Atienza
Issue Date:March 2011
pp. 1-6
Wireless body sensor networks (WBSN) hold the promise to enable next-generation patient-centric mobile-cardiology systems. A WBSN-enabled electrocardiogram (ECG) monitor consists of wearable, miniaturized and wireless sensors able to measure and wirelessly...
   
A Complete Network-On-Chip Emulation Framework
Found in: Design, Automation and Test in Europe Conference and Exhibition
By N. Genko, D. Atienza, G. De Micheli, J. M. Mendias, R. Hermida, F. Catthoor
Issue Date:March 2005
pp. 246-251
Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. NoCs can have regular...
 
Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms
Found in: IEEE Design & Test of Computers
By V. Rana,A. Nacci,I. Beretta,M. Santambrogio,D. Atienza,D. Sciuto
Issue Date:October 2012
pp. 1
Traditionally, parallel implementations of multimedia algorithms are carried out manually, since the automation of this task is very difficult due to the complex dependencies that generally exist between different elements of the data set. Moreover, there ...
 
Multi-core architecture design for ultra-low-power wearable health monitoring systems
Found in: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012)
By A. Y. Dogan,J. Constantin,M. Ruggiero,A. Burg,D. Atienza
Issue Date:March 2012
pp. 988-993
Personal health monitoring systems can offer a cost-effective solution for human healthcare. To extend the lifetime of health monitoring systems, we propose a near-threshold ultra-low-power multi-core architecture featuring low-power cores, yet capable of ...
 
Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications
Found in: Design, Automation and Test in Europe Conference and Exhibition
By A. Bartzas, S. Mamagkakis, G. Pouiklis, D. Atienza, F. Catthoor, D. Soudris, A. Thanailakis
Issue Date:March 2006
pp. 161
Network applications are becoming increasingly popular in the embedded systems domain requiring high performance, which leads to high energy consumption. In networks is observed that due to their inherent dynamic nature the dynamic memory subsystem is a ma...
 
A high-performance parallel implementation of the Chambolle algorithm
Found in: 2011 Design, Automation & Test in Europe
By A Akin,I Beretta,A A Nacci,V Rana,M D Santambrogio,D Atienza
Issue Date:March 2011
pp. 1-6
The determination of the optical flow is a central problem in image processing, as it allows to describe how an image changes over time by means of a numerical vector field. The estimation of the optical flow is however a very complex problem, which has be...
   
Towards thermally-aware design of 3D MPSoCs with inter-tier cooling
Found in: 2011 Design, Automation & Test in Europe
By M M Sabry,A Sridhar,D Atienza,Y Temiz,Y Leblebici,S Szczukiewicz,N Borhani,J R Thome,T Brunschwiler,B Michel
Issue Date:March 2011
pp. 1-6
New tendencies envisage 3D Multi-Processor System-On-Chip (MPSoC) design as a promising solution to keep increasing the performance of the next-generation high-performance computing (HPC) systems. However, as the power density of HPC systems increases with...
   
3D Thermal-aware floorplanner for many-core single-chip systems
Found in: Latin American Test Workshop
By D. Cuesta,J. L. Risco-Martin,J. L. Ayala,D. Atienza
Issue Date:March 2011
pp. 1-6
Heat removal and power density distribution delivery have become two major reliability concerns in 3D stacked technology. In this paper, we propose a thermal-driven 3D floor-planner. Our contributions include: (1) a novel multi-objective formulation to con...
 
Readiness of Computer Engineering Students of TIPQC to Online Learning
Found in: Computer and Electrical Engineering, International Conference on
By Maria Cecilia D. Atienza-Venal
Issue Date:December 2009
pp. 231-235
Today’s trend and most popular alternative medium of education is online or electronic learning. The term, electronic learning (e-learning), is being used to all types of technology-enhanced learning through the use of computers, digital technology, intern...
 
Designing Application-Specific Networks on Chips with Floorplan Information
Found in: Computer-Aided Design, International Conference on
By S. Murali, P. Meloni, F. Angiolini, D. Atienza, S. Carta, L. Benini, G. De Micheli, L. Raffo
Issue Date:November 2006
pp. 355-362
With increasing communication demands of processor and memory cores in systems on chips (SoCs), scalable networks on chips (NoCs) are needed to interconnect the cores. For the use of NoCs to be feasible in today's industrial designs, a custom-tailored, app...
 
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