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Displaying 1-28 out of 28 total
Knowledge-Guided Methodology for Third-Party Soft IP Analysis
Found in: 2014 27th International Conference on VLSI Design
By Bhanu Singh,Arunprasath Shankar,Francis Wolff,Daniel Weyer,Christos Papachristou,Bhanu Negi
Issue Date:January 2014
pp. 246-251
In System-on-Chip designs, third party IP reuse is prevalent as it increases productivity and reduces time-to-market. These IPs can be classified as untrusted designs since the user has no insight into IP verification or quality control process. In practic...
 
NEFCIS: Neuro-fuzzy Concept Based Inference System for Specification Mining
Found in: 2013 IEEE 25th International Conference on Tools with Artificial Intelligence (ICTAI)
By Arunprasath Shankar,Bhanu Pratap Singh,Francis Wolff,Christos Papachristou
Issue Date:November 2013
pp. 337-343
In a component based engineering approach, a system can be envisioned as an assembly of reusable and independently developed components. In order to produce automated tools to support the selection and assembly of components, precise selection and retrieva...
 
Knowledge-Guided Methodology for Specification Analysis
Found in: 2013 IEEE 25th International Conference on Tools with Artificial Intelligence (ICTAI)
By Bhanu Singh,Arunprasath Shankar,Yuriy Shiyanovskii,Francis Wolff,Christos Papachristou,Daniel Weyer,Steve Clay,Jim Morrison
Issue Date:November 2013
pp. 749-754
The number of Soft-IP vendors and designsbecoming available on the global market is growing at aphenomenal rate. The current practice of evaluating Soft IPsusing their specification is a time consuming manual process. A specification document is primarily ...
 
Expert System Simulation of Hardware
Found in: 2013 IEEE 25th International Conference on Tools with Artificial Intelligence (ICTAI)
By Lawrence Leinweber,Bhanu Singh,Christos Papachristou
Issue Date:November 2013
pp. 207-212
Hardware lint tools based on static analysis techniquesonly check for structural, coding and consistency problemsin RTL code. They have the limitation that they do notperform behavioral analysis and have a predefined rule-basethat is not enhanced by users ...
 
Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis
Found in: IEEE Transactions on Computers
By Seetharam Narasimhan,Dongdong Du,Rajat Subhra Chakraborty,Somnath Paul,Francis G. Wolff,Christos A. Papachristou,Kaushik Roy,Swarup Bhunia
Issue Date:November 2013
pp. 2183-2195
Hardware Trojan attack in the form of malicious modification of a design has emerged as a major security threat. Side-channel analysis has been investigated as an alternative to conventional logic testing to detect the presence of hardware Trojans. However...
 
Fast and compact binary-to-BCD conversion circuits for decimal multiplication
Found in: Computer Design, International Conference on
By Osama Al-Khaleel,Zakaria Al-Qudah,Mohammad Al-Khaleel,Christos A. Papachristou,Francis G. Wolff
Issue Date:October 2011
pp. 226-231
Decimal arithmetic has received considerable attention recently due to its suitability for many financial and commercial applications. In particular, numerous algorithms have been recently proposed for decimal multiplication. A major approach to decimal mu...
 
An Improved Algorithm to Smooth Delay Jitter in Cyber-Physical Systems
Found in: Scalable Computing and Communications; International Conference on Embedded Computing, International Conference on
By Huthaifa Al-Omari, Francis Wolff, Christos Papachristou, David McIntyre
Issue Date:September 2009
pp. 81-86
Delay jitter is a critical factor that must be considered in networked real-time applications that require accurate prediction of packet delivery times. Delay jitter can be smoothed by holding packets in a play-back buffer for a certain time called a play-...
 
Avoiding Delay Jitter in Cyber-Physical Systems Using One Way Delay Variations Model
Found in: Computational Science and Engineering, IEEE International Conference on
By Huthaifa Al-Omari, Francis Wolff, Christos Papachristou, David McIntyre
Issue Date:August 2009
pp. 295-302
Delay jitter adversely affects the performance ofnetworked real-time applications that require accurate prediction of packet delivery times. Delay jitter can be smoothed by holding packets in a play-back buffer for a certain time called a playback delay. I...
 
Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?
Found in: On-Line Testing Symposium, IEEE International
By Abhijit Chatterjee, Jacob Abraham, Adit Singh, Elie Maricau, Rakesh Kumar, Christos Papachristou
Issue Date:June 2009
pp. 129
There has been ongoing debate regarding the use of voltage overscaling along with error resilience techniques for ultra low power operation of scaled CMOS logic. The issue is whether to build enough design margin into future electronic systems so that erro...
 
A Reconfigurable SoC Architecture and Caching Scheme for 3D Medical Image Processing
Found in: Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
By Jianchun Li, Christos Papachristou, Raj Shekhar
Issue Date:April 2004
pp. 320-321
In this paper, we present a reconfigurable SoC (system-on-chip) architecture and a 3D caching scheme, targeted to Virtex II Pro FPGAs, to accelerate a broad range of 3D medical imaging algorithms, typically dominated by local operations. To achieve high co...
   
Improving Bus Test via IDDT and Boundary Scan
Found in: Design Automation Conference
By Massood Tabib-Azar, Christos A. Papachristou, Shih-Yu Yang
Issue Date:June 2001
pp. 307-312
This paper presents a systematic test methodology targeting bus line interconnect defects using IDDT testing and Boundary Scan. Traditional test is unable to detect all possible defects, especially timing-related faults. Open and short defects on interconn...
 
An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing
Found in: Test Conference, International
By Mehrdad Nourani, Christos Papachristou
Issue Date:October 2000
pp. 902
We present an optimization method that complies with IEEE P1500 draft standard and deals with modeling and design of the test access mechanism for the SoCs. The basic goal is to develop a global design for test methodology and optimization technique for te...
 
Instruction Randomization Self Test For Processor Cores
Found in: VLSI Test Symposium, IEEE
By Ken Batcher, Christos Papachristou
Issue Date:April 1999
pp. 34
Access to embedded processor cores for application of test has greatly complicated the testability of large systems on silicon. Scan based testing methods cannot be applied to processor cores which cannot be modified to meet the design requirements for sca...
 
Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Joan Carletta, Mehrdad Nourani, Christos Papachristou
Issue Date:March 1999
pp. 278
This work facilitates the testing of datapath-controller pairs in an integrated fashion, with datapath and controller tested together in a single test session. Such an approach requires less test overhead than an approach that isolates datapath and control...
 
Testability Enhancement for Behavioral Descriptions Containing Conditional Statements
Found in: Test Conference, International
By Kelly A. Ockunzzi, Christos A. Papachristou
Issue Date:November 1997
pp. 236
A high-level test synthesis methodology based on BIST is proposed. This methodology targets the conditional if-then-else statements in a behavioral description because such statements can introduce testability problems in the resulting circuit. How well th...
 
BIST Testability Enhancement of System Level Circuits : Experience with An Industrial Design
Found in: Asian Test Symposium
By Kowen Lai, Christos A. Papachristou
Issue Date:November 1996
pp. 219
A systematic methodology for testability analysis and enhancement of sequential circuit designs using Built-In Self-Test (BIST) is described. Inter-modular test insertions is applied to improve controllability as well as observability in a system level cir...
 
False Path Exclusion in Delay Analysis of RTL-Based Datapath-Controller Designs
Found in: European Design Automation Conference with EURO-VHDL
By Christos A. Papachristou, Mehrdad Nourani
Issue Date:September 1996
pp. 0336
C. Papachristou, M. Nourani Abstract: We present an accurate delay estimation algorithm at the register transfer level. We introduce
 
Accelerating mutual information-based 3D medical image registration with An FPGA computing platform (abstract only)
Found in: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays (FPGA '05)
By Christos Papachristou, Jianchun Li, Raj Shekhar
Issue Date:February 2005
pp. 279-279
Mutual information-based 3D image Registration algorithm is shown to be an accurate, robust and more general registration method for medical image processing. However, its potential application in clinic is jeopardized by its high computational costs. Like...
     
Improving bus test via IDDT and boundary scan
Found in: Proceedings of the 38th conference on Design automation (DAC '01)
By Christos A. Papachristou, Massood Tabib-Azar, Shih-Yu Yang
Issue Date:June 2001
pp. 307-312
This paper presents a systematic test methodology targeting bus line interconnect defects using IDDT testing and Boundary Scan. Traditional test is unable to detect all possible defects, especially timing-related faults. Open and short defects on interconn...
     
Synthesis-for-testability of controller-datapath pairs that use gated clocks
Found in: Proceedings of the 37th conference on Design automation (DAC '00)
By Christos Papachristou, Joan Carletta, Mehrdad Nourani
Issue Date:June 2000
pp. 613-618
A method for high level synthesis-for-testability of controller-datapath pairs that use gated clocks is developed. It uses a register allocation technique that improves the observability of the controller through the datapath, and takes advantage of the un...
     
Synthesis of controllers for full testability of integrated datapath-controller pairs
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '99)
By Christos Papachristou, Joan Carletta, Mehrdad Nourani
Issue Date:January 1999
pp. 58-es
In this paper, we consider the new and evocative work on tangible interfaces and the issues this raises in the light of some old lessons of HCI. In doing so, we make the point that many of these lessons of good design still apply, even when we are consider...
     
Integrated test of interacting controllers and datapaths
Found in: ACM Transactions on Design Automation of Electronic Systems (TODAES)
By Christos Papachristou, Joan Carletta, Mehrdad Nourani
Issue Date:January 1996
pp. 401-422
In systems consisting of interacting datapaths and controllers and utilizing built-in self test (BIST), the datapaths and controllers are traditionally tested separately by isolating each component from the environment of the system during test. This work ...
     
A multiple clocking scheme for low power RTL design
Found in: Proceedings of the 1995 international symposium on Low power design (ISLPED '95)
By Christos Papachristou, Mark Spining, Mehrdad Nourani
Issue Date:April 1995
pp. 27-32
Sophisticated binary translators and dynamic optimizers demand a program profiler with low overhead, high accuracy, and the ability to collect a variety of profile types. A profiling scheme that achieves these goals is proposed. Conceptually, the hardware ...
     
An approach for redesigning in data path synthesis
Found in: Proceedings of the 30th international on Design automation conference (DAC '93)
By Christos Papachristou, Haidar Harmanani, Mehrdad Nourani
Issue Date:June 1993
pp. 419-423
A new gridless router accelerated by Content Addressable Memory (CAM) is presented. A gridless version of the line-expansion algorithm is implemented, which always finds a path if one exists. The router runs in linear time by means of the CAM-based acceler...
     
A layout estimation algorithm for RTL datapaths
Found in: Proceedings of the 30th international on Design automation conference (DAC '93)
By Christos Papachristou, Mehrdad Nourani
Issue Date:June 1993
pp. 285-291
A new gridless router accelerated by Content Addressable Memory (CAM) is presented. A gridless version of the line-expansion algorithm is implemented, which always finds a path if one exists. The router runs in linear time by means of the CAM-based acceler...
     
A data path synthesis method for self-testable designs
Found in: Proceedings of the 28th conference on ACM/IEEE design automation conference (DAC '91)
By Christos A. Papachristou, Haidar Harmanani, Scott Chiu
Issue Date:June 1991
pp. 378-384
A new gridless router accelerated by Content Addressable Memory (CAM) is presented. A gridless version of the line-expansion algorithm is implemented, which always finds a path if one exists. The router runs in linear time by means of the CAM-based acceler...
     
A design for testability scheme with applications to data path synthesis
Found in: Proceedings of the 28th conference on ACM/IEEE design automation conference (DAC '91)
By Christos A. Papachristou, Scott Chiu
Issue Date:June 1991
pp. 271-277
A new gridless router accelerated by Content Addressable Memory (CAM) is presented. A gridless version of the line-expansion algorithm is implemented, which always finds a path if one exists. The router runs in linear time by means of the CAM-based acceler...
     
Expert system approach to VLSI cell design (abstract)
Found in: Proceedings of the 1986 ACM fourteenth annual conference on Computer science (CSC '86)
By Christos A. Papachristou
Issue Date:February 1986
pp. 485
A description of an advanced graphics interface design that provides the applications developer with a very high level graphics environment is presented. The object oriented design is shown to be appropriate to achieving device and implementation independe...
     
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