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Displaying 1-29 out of 29 total
An Adaptable Task Manager for Reconfigurable Architecture Kernels
Found in: Adaptive Hardware and Systems, NASA/ESA Conference on
By Yuriy Shiyanovskii, Francis Wolff, Chris Papachristou, Dan Weyer
Issue Date:August 2009
pp. 132-137
Self-reconfigurable hardware is a new emerging technology which will enable adaptation of computing systems to changing environments.This paper deals with the design of architecture kernels for an autonomous on-board system and the development of an adapta...
 
SRAM cell design using tri-state devices for SEU protection
Found in: On-Line Testing Symposium, IEEE International
By Yuriy Shiyanovskii, Frank Wolff, Chris Papachristou
Issue Date:June 2009
pp. 114-119
A new SRAM cell model, SRAMT, is presented providing a scalable solution to soft error for various energy levels of protection with minimal power consumption and write time penalties. Our model is based on a classic 6 transistor inner core SRAM cell and an...
 
SRAM Cell Design Protected from SEU Upsets
Found in: On-Line Testing Symposium, IEEE International
By Yuriy Shiyanovskii, Francis Wolff, Chris Papachristou
Issue Date:July 2008
pp. 169-170
There have been many solutions to create a soft error immuneSRAM cell. These solutions can be broken down intothree categories: a) hardening, b) recovery, c) protection.Hardening techniques insert circuitry in an SRAM cell possiblyduplicating the number of...
 
Extended abstract: An embedded flash memory vault for software Trojan protection
Found in: Hardware-Oriented Security and Trust, IEEE International Workshop on
By Francis Wolff, Chris Papachristou, David McIntyre, Daniel Weyer, William Clay
Issue Date:June 2008
pp. 97-99
The protection from software Trojans in embedded systems is a difficult problem. The only way a software Trojan can be inserted into an embedded system is if the embedded systems instruction code is behaviorally modified. Trojans can be introduced into the...
 
Face Recognition using a Cognitive Processing Model
Found in: Adaptive Hardware and Systems, NASA/ESA Conference on
By Gorn Tepvorachai, Chris Papachristou
Issue Date:June 2008
pp. 505-512
In the conventional eigenface method, the principle component analysis (PCA) algorithm associates the Eigen vectors with the changes in illumination. In this paper, we propose an improvement of facial image association for face recognition using a cognitiv...
 
Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Francis Wolff, Chris Papachristou, Swarup Bhunia, Rajat S. Chakraborty
Issue Date:March 2008
pp. 1362-1365
There have been serious concerns recently about the security of microchips from hardware trojan horse insertion during manufacturing. This issue has been raised recently due to outsourcing of the chip manufacturing processes to reduce cost. This is an impo...
 
A Configurable FIR Filter Scheme based on an Adaptive Multilayer Network Structure
Found in: Adaptive Hardware and Systems, NASA/ESA Conference on
By Gorn Tepvorachai, Chris Papachristou
Issue Date:August 2007
pp. 176-183
In this paper, we present a design technique of configurable FIR filter architecture based on neural network like (multilayer network) structure. This architecture is a generalization of the configurable adaptive FIR filters and can be implemented on an FP...
 
Facial Image Associative Memory Model
Found in: Adaptive Hardware and Systems, NASA/ESA Conference on
By Gorn Tepvorachai, Chris Papachristou
Issue Date:August 2007
pp. 233-242
Facial image associative memory takes a facial input image and returns associated faces pre-embedded in memory. This paper proposes a three-phase implementation process: a) sensory pre-processing, b) information interfusion, and c) association with existin...
 
An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding
Found in: On-Line Testing Symposium, IEEE International
By Osama Al-Khaleel, Chris Papachristou, Francis Wolff, Kiamal Pekmestzi
Issue Date:July 2007
pp. 71-78
In this paper we present an efficient design technique for implementing the Elliptic Curve Cryptographic (ECC) Scheme in FPGAs. Our technique is based on a novel and efficient implementation of modular multiplication which is the core operation of ECC. To ...
 
Self-Configurable Neural Network Processor for FIR Filter Applications
Found in: Adaptive Hardware and Systems, NASA/ESA Conference on
By Gorn Tepvorachai, Chris Papachristou
Issue Date:June 2006
pp. 114-121
A self-configurable system is one that is designed primarily for the purpose of reconfigurable control and adaptive signal processing. It evolves by restructures and readjustments back and forth which can track the environment and the system variation in t...
 
A Large Scale Adaptable Multiplier for Cryptographic Applications
Found in: Adaptive Hardware and Systems, NASA/ESA Conference on
By Osama Al-Khaleel, Chris Papachristou, Frank Wolff, Kiamal Pekmestzi
Issue Date:June 2006
pp. 477-484
Large multipliers are important for cryptographic applications because they need large keys. The ability to modify key lengths, for security reasons, suggests adaptability in multiplication bit-length. However, reconfigurability of multiplication is a diff...
 
Radiation Induced Single-Word Multiple-Bit Upsets Correction in SRAM
Found in: On-Line Testing Symposium, IEEE International
By Balkaran Gill, Michael Nicolaidis, Chris Papachristou
Issue Date:July 2005
pp. 266-271
In this paper, we introduce an approach for Single-word Multiple-bit Upsets (SMU) correction in SRAM. This approach uses the combination of Built in Current Sensor (BICS) and Hamming Single Error Correction/Double Error Detection (SEC/DED) codes. The BICS ...
 
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Balkaran Gill, Michael Nicolaidis, Francis Wolff, Chris Papachristou, Steven Garverick
Issue Date:March 2005
pp. 592-597
In this paper we propose a new Built in Current Sensor (BICS) to detect single event upsets in SRAM. The BICS is designed and validated for 100nm process technology. The BICS reliability analysis for process, voltage, temperature, and power supply noise ar...
 
Soft Delay Error Effects in CMOS Combinational Circuits
Found in: VLSI Test Symposium, IEEE
By Balkaran S. Gill, Chris Papachristou, Francis G. Wolff
Issue Date:April 2004
pp. 325
Single event upsets (SEUs) are due to high energetic particle strike at sensitive nodes of CMOS combinational circuits. In this paper, we introduce a type of soft errors which manifests as soft delay. The soft delay is temporary delay in CMOS combinational...
 
Test Compression and Hardware Decompression for Scan-Based SoCs
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Francis G. Wolff, Chris Papachristou, David R. McIntyre
Issue Date:February 2004
pp. 10716
We present a new decompression architecture suitable for embedded cores in SoCs which focuses on improving the download time by avoiding higher internal-to-ATE clock ratios and by exploiting hardware parallelism. The Bounded Huffman compression facilitates...
   
Designing Self Test Programs for Embedded DSP Cores
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Hani Rizk, Chris Papachristou, Francis Wolff
Issue Date:February 2004
pp. 20816
This paper describes a self test program design technique for embedded DSP cores. The method requires minimal knowledge of the core?s internals and minimal insertion of external LFSR hardware, without scan insertions. The test program consists of a small s...
 
A Technique for High Ratio LZW Compression
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Michael J. Knieser, Francis G. Wolff, Chris A. Papachristou, Daniel J. Weyer, David R. McIntyre
Issue Date:March 2003
pp. 10116
Reduction of both the test suite size and the download time of test vectors is important in today's System-On-a-Chip designs. In this paper, a method for compressing the scan test patterns using the LZW algorithm is presented. This method leverages the lar...
 
Multiscan-Based Test Compression and Hardware Decompression Using LZ77
Found in: Test Conference, International
By Francis G. Wolff, Chris Papachristou
Issue Date:October 2002
pp. 331
In this paper we present a new test data compression technique and an associated decompression scheme for testing VLSI chips. Our method is based on our novel use of the much utilized in software LZW, particularly LZ77 algorithm. We adapt LZ77 to accommoda...
 
Test Strategies for BIST at the Algorithmic and Register-Transfer Levels
Found in: Design Automation Conference
By Chris Papachristou, Kelly A. Ockunzzi
Issue Date:June 2001
pp. 65-70
The proposed BIST-based DFT method target testability problems caused by three constructs. The first construct is reconvergent fanout in a circuit behavior, which causes correlation. The second construct, control statements, also cause correlation and rela...
 
Breaking Correlation to Improve Testability
Found in: VLSI Test Symposium, IEEE
By Kelly Ockunzzi, Chris Papachristou
Issue Date:April 2001
pp. 0075
A BIST-based design-for-test method targeting correlation in circuit behaviors is proposed. Correlation introduced by reconvergent fanout and conditional statements is considered. Testability problems caused by correlation are described and behavioral modi...
 
Using Codesign Techniques to Support Analog Functionality
Found in: Hardware/Software Co-Design, International Workshop on
By Francis G. Wolff, Michael J. Knieser, Dan J. Weyer, Chris A. Papachristou
Issue Date:May 1999
pp. 79
With the growth of System on a Chip (SoC), the functionality of analog components must also be considered in the design process. This paper describes some of the design implementation partitioning issues and experiences using analog and digital techniques ...
 
A Method of Distributed Controller Design for RTL Circuits
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Chris Papachristou, Yusuf Alzazeri
Issue Date:March 1999
pp. 774
This paper describes a design or redesign technique to reduce the control path delay and thus improve the performance of an RTL circuit. The basic Idea is to replace an existing centralized controller of an RTL circuit with a distributed controller structu...
 
Testing DSP Cores Based on Self-Test Programs
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Wei Zhao, Chris Papachristou
Issue Date:February 1998
pp. 166
This paper presents a new method for the testing of the datapath of DSP cores based on self-test program. During the test, random patterns are loaded into the core, exercise different components of the core, and then are loaded out of the core for observat...
 
A high-speed radix-4 multiplexer-based array multiplier
Found in: Proceedings of the 18th ACM Great Lakes symposium on VLSI (GLSVLSI '08)
By Chris Papachristou, Dimitris Bekiaris, Kiamal Pekmestzi
Issue Date:May 2008
pp. 1-37
This paper presents a new radix-4 multiplexer-based array multiplier, based on a multiplication scheme shown in a previous work, where 4-to-1 multiplexers are used for the computation of partial products. In the proposed design, the rows of the array are r...
     
Towards trojan-free trusted ICs: problem analysis and detection scheme
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '08)
By Chris Papachristou, Francis Wolff, Rajat S. Chakraborty, Swarup Bhunia
Issue Date:March 2008
pp. 1-30
There have been serious concerns recently about the security of microchips from hardware trojan horse insertion during manufacturing. This issue has been raised recently due to outsourcing of the chip manufacturing processes to reduce cost. This is an impo...
     
Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '07)
By Balkaran S. Gill, Chris Papachristou, Francis G. Wolff
Issue Date:April 2007
pp. 1460-1465
Soft errors in semiconductor memories occur due to charged particle strikes at the cell nodes. In this paper, we present a new asymmetric memory cell to increase the soft error tolerance of SRAM. At the same time, this cell can be used at the reduced suppl...
     
Test strategies for BIST at the algorithmic and register-transfer levels
Found in: Proceedings of the 38th conference on Design automation (DAC '01)
By Chris Papachristou, Kelly A. Ockunzzi
Issue Date:June 2001
pp. 65-70
The proposed BIST-based DFT method target testability problems caused by three constructs. The first construct is reconvergent fanout in a circuit behavior, which causes correlation. The second construct, control statements, also cause correlation and rela...
     
Using codesign techniques to support analog functionality
Found in: Proceedings of the seventh international workshop on Hardware/software codesign (CODES '99)
By Chris A. Papachristou, Dan J. Weyer, Francis G. Wolff, Michael J. Knieser
Issue Date:March 1999
pp. 79-84
We present a parallel implementation of the Buckshot document clustering algorithm. We demonstrate that this parallel approach is highly efficient both in terms of load balancing and minimization of communication. In a series of experiments using the 2GB o...
     
A method of distributed controller design for RTL circuits
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '99)
By Chris Papachristou, Yusuf Alzazeri
Issue Date:January 1999
pp. 48-es
In this paper, we consider the new and evocative work on tangible interfaces and the issues this raises in the light of some old lessons of HCI. In doing so, we make the point that many of these lessons of good design still apply, even when we are consider...
     
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