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Displaying 1-27 out of 27 total
TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique
Found in: Quality Electronic Design, International Symposium on
By Kee-Jong Kim, Chris H. Kim, Kaushik Roy
Issue Date:March 2005
pp. 59-64
We propose a novel low power Charge Recycling SRAM (CR-SRAM) for portable TFT-LCD applications. In portable TFT-LCD applications, low power considerations are becoming more important for longer battery lifetime. For reducing the power consumption in SRAMs,...
 
Process and Reliability Sensors for Nanoscale CMOS
Found in: IEEE Design & Test of Computers
By John P. Keane,Chris H. Kim,Qunzeng Liu,Sachin S. Sapatnekar
Issue Date:October 2012
pp. 8-17
Editor's notes:
 
An on-chip NBTI sensor for measuring PMOS threshold voltage degradation
Found in: Low Power Electronics and Design, International Symposium on
By John Keane, Tae-Hyoung Kim, Chris H. Kim
Issue Date:August 2007
pp. 189-194
Negative Bias Temperature Instability (NBTI) is one of the most critical device reliability issues facing scaled CMOS technology. In order to better understand the characteristics of this mechanism, accurate and efficient means of measuring its effects mus...
 
Nanoscale Memories Pose Unique Challenges
Found in: IEEE Design and Test of Computers
By Chris H. Kim, Leland Chang
Issue Date:January 2011
pp. 6-8
<p>This special issue presents seven articles that examine the characteristics, capabilities, and challenges of various embedded memories, especially those designed in emerging technologies. The articles address the intricacies and trade-offs require...
 
A multi-story power delivery technique for 3D integrated circuits
Found in: Low Power Electronics and Design, International Symposium on
By Pulkit Jain, Tae-Hyoung Kim, John Keane, Chris H. Kim
Issue Date:August 2008
pp. 57-62
Integrating circuits in the vertical direction can alleviate interconnect related problems and enable heterogeneous chips to be stacked in a single package with a small form factor. This paper addresses the power delivery issues in 3D chips revealing some ...
 
Leakage in Nano-Scale Technologies: Mechanisms, Impact and Design Considerations
Found in: Design Automation Conference
By Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy
Issue Date:June 2004
pp. 6-11
The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness are scaled. Consequently, the identification of different leakage componen...
 
Impact of NBTI on SRAM Read Stability and Design for Reliability
Found in: Quality Electronic Design, International Symposium on
By Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
Issue Date:March 2006
pp. 210-218
Negative Bias Temperature Instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious effects on transistor threshold voltage. The degradation of PMOS devices due to ...
 
Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations
Found in: 2014 27th International Conference on VLSI Design
By Ayan Paul,Chaitanya Kshirsagar,Sachin S. Sapatnekar,Steven Koester,Chris H. Kim
Issue Date:January 2014
pp. 399-404
In this paper we propose a generic approach to statistically model leakage variation of devices with steep sub-threshold slope caused by random threshold variations. Monte Carlo simulation results based on our model show less than 11% error in 6&amp;si...
 
A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM
Found in: Low Power Electronics and Design, International Symposium on
By Ki Chul Chun, Pulkit Jain, Chris H. Kim
Issue Date:August 2009
pp. 119-120
A logic-compatible low power eDRAM is demonstrated in 65nm CMOS achieving a retention time of 1.25msec and a static power dissipation of 91.3µW/Mb at 0.9V, 85ºC. A boosted 3T gain cell enhances data retention time and read speed. A regulated bit-line write...
 
Sleep transistor sizing and control for resonant supply noise damping
Found in: Low Power Electronics and Design, International Symposium on
By Jie Gu, Hanyong Eom, Chris H. Kim
Issue Date:August 2007
pp. 80-85
A fact that has generally been unnoticed is that sleep transistors for leakage reduction can significantly damp the resonant supply noise due to their series resistance. This paper describes an optimal sleep transistor sizing method considering the dominan...
 
Modeling Subthreshold Leakage Current in General Transistor Networks
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Paulo F Butzen, Andre I. Reis, Chris H. Kim, Renato P. Ribas
Issue Date:March 2007
pp. 512-513
An improved model for subthreshold leakage current in general transistor networks is proposed. Previous modeling, presented in the literature and originally focused on series-parallel topologies, has been extended to non-series-parallel device arrangements...
 
Self Calibrating Circuit Design for Variation Tolerant VLSI Systems
Found in: On-Line Testing Symposium, IEEE International
By Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy
Issue Date:July 2005
pp. 100-105
Increasing leakage current and aggravating process variations are showing impact on dynamic circuit performance and robustness as technology scales into the nanometer regime. This paper describes a self-calibrating process compensating dynamic (PCD) circui...
 
Larger-than-Vdd Forward Body Bias in Sub-0.5V Nanoscale CMOS
Found in: Low Power Electronics and Design, International Symposium on
By Hari Ananthan, Chris H. Kim, Kaushik Roy
Issue Date:August 2004
pp. 8-13
This paper examines the effectiveness of larger-than-Vdd forward body bias (FBB) in nanoscale bulk CMOS circuits where Vdd is expected to scale below 0.5V. Equal-to and larger-than Vdd FBB schemes offer unique advantages over conventional FBB such as simpl...
 
Silicon Odometers: Compact In-situ Aging Sensors for Robust System Design
Found in: IEEE Micro
By Xiaofei Wang,John Keane,Tony Tae-Hyoung Kim,Pulkit Jain,Qianying Tang,Chris H. Kim
Issue Date:February 2014
pp. 1
Circuit reliability issues such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), Time Dependent Dielectric Breakdown (TDDB) Electromigration (EM), and Random Telegraph Noise (RTN) have become a growing concern with technology scaling. Pr...
 
Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications
Found in: Proceedings of the International Conference on Computer-Aided Design (ICCAD '12)
By Bongjin Kim, Chris H. Kim, Pingqiang Zhou, Sachin S. Sapatnekar, Won Ho Choi
Issue Date:November 2012
pp. 263-270
On-chip switched-capacitor (SC) DC-DC converters have recently been demonstrated in silicon for high-performance applications such as multicore processors. The efficiency of the power delivery system using SC converters is a major concern, but this has not...
     
A multi-story power delivery technique for 3D integrated circuits
Found in: Proceeding of the thirteenth international symposium on Low power electronics and design (ISLPED '08)
By Chris H. Kim, John Keane, Pulkit Jain, Tae-Hyoung Kim
Issue Date:August 2008
pp. 383-384
Integrating circuits in the vertical direction can alleviate interconnect related problems and enable heterogeneous chips to be stacked in a single package with a small form factor. This paper addresses the power delivery issues in 3D chips revealing some ...
     
An on-chip NBTI sensor for measuring PMOS threshold voltage degradation
Found in: Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)
By Chris H. Kim, John Keane, Tae-Hyoung Kim
Issue Date:August 2007
pp. 189-194
Negative Bias Temperature Instability (NBTI) is one of the most critical device reliability issues facing scaled CMOS technology. In order to better understand the characteristics of this mechanism, accurate and efficient means of measuring its effects mus...
     
Variation aware performance analysis of gain cell embedded DRAMs
Found in: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design (ISLPED '10)
By Chris H. Kim, Ki Chul Chun, Wei Zhang
Issue Date:August 2010
pp. 19-24
Gain cell embedded DRAMs are twice as dense as 6T SRAMs, are logic compatible, have decoupled read and write paths providing good low voltage margin, and can drive long bitlines with gain. In this work, we present a variation study of gain cell eDRAM perfo...
     
A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM
Found in: Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design (ISLPED '09)
By Chris H. Kim, Ki Chul Chun, Pulkit Jain
Issue Date:August 2009
pp. 1-2
A logic-compatible low power eDRAM is demonstrated in 65nm CMOS achieving a retention time of 1.25msec and a static power dissipation of 91.3µW/Mb at 0.9V, 85ºC. A boosted 3T gain cell enhances data retention time and read speed. A regulated bit-...
     
Sleep transistor sizing and control for resonant supply noise damping
Found in: Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)
By Chris H. Kim, Hanyong Eom, Jie Gu
Issue Date:August 2007
pp. 80-85
A fact that has generally been unnoticed is that sleep transistors for leakage reduction can significantly damp the resonant supply noise due to their series resistance. This paper describes an optimal sleep transistor sizing method considering the dominan...
     
NBTI-aware synthesis of digital circuits
Found in: Proceedings of the 44th annual conference on Design automation (DAC '07)
By Chris H. Kim, Sachin S. Sapatnekar, Sanjay V. Kumar
Issue Date:June 2007
pp. 370-375
Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a major reliability concern in nanometer scale design, causing the temporal degradation of the threshold voltage of the PMOS transistors, and the delay of digital circuits. A novel...
     
Modeling and estimating leakage current in series-parallel CMOS networks
Found in: Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI (GLSVLSI '07)
By Andre I. Reis, Chris H. Kim, Paulo F. Butzen, Renato P. Ribas
Issue Date:March 2007
pp. 269-274
This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networks, ignored by previous works, is considered in static current analysis. Both...
     
An analytical model for negative bias temperature instability
Found in: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design (ICCAD '06)
By Chris H. Kim, Sachin S. Sapatnekar, Sanjay V. Kumar
Issue Date:November 2006
pp. 493-496
Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a significant reliability concern in present day digital circuit design. With continued scaling, the effect of NBTI has rapidly grown in prominence, forcing designers to resort to ...
     
A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boosting
Found in: Proceedings of the 2006 international symposium on Low power electronics and design (ISLPED '06)
By Chris H. Kim, Jie Gu, Jonggab Kil
Issue Date:October 2006
pp. 67-72
This paper describes an interconnect technique for sub-threshold circuits to improve global wire delay and reduce the delay variation due to PVT fluctuations. By internally boosting the gate voltage of the driver transistors, operating region is shifted fr...
     
Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems
Found in: Proceedings of the 2006 conference on Asia South Pacific design automation (ASP-DAC '06)
By Chris H. Kim, Sachin S. Sapatnekar, Sanjay V. Kumar
Issue Date:January 2006
pp. 559-564
Process variations and temperature variations can cause both the frequency and the leakage of the chip to vary significantly from their expected values, thereby decreasing the yield. Adaptive Body Bias (ABB) can be used to pull back the chip to the nominal...
     
Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS
Found in: Proceedings of the 2004 international symposium on Low power electronics and design (ISLPED '04)
By Chris H. Kim, Hari Ananthan, Kaushik Roy
Issue Date:August 2004
pp. 8-13
This paper examines the effectiveness of larger-than-Vdd forward body bias (FBB) in nanoscale bulk CMOS circuits where Vdd is expected to scale below 0.5V. Equal-to and larger-than Vdd FBB schemes offer unique advantages over conventional FBB such as simpl...
     
Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors
Found in: Proceedings of the 2002 international symposium on Low power electronics and design (ISLPED '02)
By Chris H. Kim, Kaushik Roy
Issue Date:August 2002
pp. 251-254
This paper presents a Dynamic Vt SRAM (DTSRAM) architecture to reduce the subthreshold leakage in cache memories. The Vt of each cache line is controlled separately by means of body biasing. In order to minimize the energy and delay overhead, a cache line ...
     
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