Search For:

Displaying 1-11 out of 11 total
Monolithic Silicon Waveguides in Standard Silicon
Found in: IEEE Micro
By Chia-Ming Chang,Olav Solgaard
Issue Date:January 2013
pp. 32-40
A methodology allows fabrication of silicon-photonic devices in standard silicon wafers, eliminating the need for silicon-on-insulator (SOI) wafers. Using this technology, the authors demonstrate low-loss silicon waveguides (2.34 dB/cm), comparable to conv...
 
Realistic Character Motion Response in Computer Fighting Game
Found in: Multimedia, International Symposium on
By Huai-Che Lee, Chia-Ming Chang, Jui-Shiang Chao, Wei-Te Lin
Issue Date:December 2007
pp. 169-175
We present a hybrid motion response model for presenting dynamic character behavior during character interactions in computer games. The method seamlessly integrates motion captured data with physics-based character simulation. The result preserves the des...
 
State Re-Encoding for Peak Current Minimization
Found in: Computer-Aided Design, International Conference on
By Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
Issue Date:November 2006
pp. 33-38
In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the reduction of switching activities of state registers (i.e., state bits). However...
 
CFU: multi-purpose configurable filtering unit for mobile multimedia applications on graphics hardware
Found in: Proceedings of the Conference on High Performance Graphics 2009 (HPG '09)
By Chia-Ming Chang, Chih-Hao Sun, Ka-Hang Lok, Shao-Yi Chien, You-Ming Tsao
Issue Date:August 2009
pp. 1-8
In order to increase the capability of mobile GPUs in image/video processing, a multi-purpose configurable filtering unit (CFU), which is a new configurable unit for image filtering on stream processing architecture, is proposed in this paper. CFU is locat...
     
Low-power anti-aging zero skew clock gating
Found in: ACM Transactions on Design Automation of Electronic Systems (TODAES)
By Chia-Ming Chang
Issue Date:March 2013
pp. 1-37
In advanced CMOS technology, the NBTI (negative bias temperature instability) effect results in delay degradations of PMOS transistors. Further, because of clock gating, PMOS transistors in a clock tree often have different active probabilities, leading to...
     
Quorum-based key management scheme in wireless sensor networks
Found in: Proceedings of the 6th International Conference on Ubiquitous Information Management and Communication (ICUIMC '12)
By Lih-Chyau Wuu, Chi-Hsiang Hung, Chia-Ming Chang
Issue Date:February 2012
pp. 1-6
To ensure the security of wireless sensor networks, it is important to have a robust key management scheme. In this paper, we propose a Quorum-based key management scheme. A specific sensor, called as key distribution server (KDS), generates a key matrix a...
     
Opposite-phase register switching for peak current minimization
Found in: ACM Transactions on Design Automation of Electronic Systems (TODAES)
By Chia-Ming Chang, Shih-Hsu Huang, Yow-Tyng Nieh
Issue Date:January 2009
pp. 1-29
In a synchronous sequential circuit, huge current peaks are often observed at the moment of clock transition (since all registers are clocked). Previous works focus on reducing the number of switching registers. However, even though the switching registers...
     
Type-matching clock tree for zero skew clock gating
Found in: Proceedings of the 45th annual conference on Design automation (DAC '08)
By Chia-Ming Chang, Hsin-Po Wang, Jia-Zong Lin, Shih-Hsu Huang, Yu-Sheng Lu, Yuan-Kai Ho
Issue Date:June 2008
pp. 1-30
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR gates, and buffer gates. If the logic gates at the same level are in different...
     
Clock period minimization with minimum delay insertion
Found in: Proceedings of the 44th annual conference on Design automation (DAC '07)
By Chia-Ming Chang, Chun-Hua Cheng, Shih-Hsu Huang, Yow-Tyng Nieh
Issue Date:June 2007
pp. 970-975
The combination of clock skew scheduling and delay insertion may lead to further clock period reduction. Although some previous works can minimize the clock period, they only heuristically reduce the required inserted delay. However, since the delay insert...
     
State re-encoding for peak current minimization
Found in: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design (ICCAD '06)
By Chia-Ming Chang, Shih-Hsu Huang, Yow-Tyng Nieh
Issue Date:November 2006
pp. 33-38
In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the reduction of switching activities of state registers (i.e., state bits). However...
     
Fast multi-domain clock skew scheduling for peak current reduction
Found in: Proceedings of the 2006 conference on Asia South Pacific design automation (ASP-DAC '06)
By Chia-Ming Chang, Shih-Hsu Huang, Yow-Tyng Nieh
Issue Date:January 2006
pp. 254-259
Given several specific clocking domains, the peak current minimization problem can be formulated as a 0-1 integer linear program. However, if the number of binary variables is large, the run time is unacceptable. In this paper, we study the reduction of th...
     
 1