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Displaying 1-10 out of 10 total
Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture
Found in: Computer Architecture, International Symposium on
By Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore
Issue Date:June 2003
pp. 422
This paper describes the polymorphous TRIPS architecture which can be configured for different granularities and types of parallelism. TRIPS contains mechanisms that enable the processing cores and the on-chip memory system to be configured and combined in...
 
Microarchitecture in the system-level integration era
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Charles R. Moore
Issue Date:November 2008
pp. i
No summary available.
 
Scalable Hardware Memory Disambiguation for High ILP Processors
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler
Issue Date:December 2003
pp. 399
This paper describes several methods for improving the scalability of memory disambiguation hardware for future high ILP processors. As the number of in-flight instructions grows with issue width and pipeline depth, the load/store queues (LSQ) threaten to ...
 
Scaling to the End of Silicon with EDGE Architectures
Found in: Computer
By Doug Burger, Stephen W. Keckler, Kathryn S. McKinley, Mike Dahlin, Lizy K. John, Calvin Lin, Charles R. Moore, James Burrill, Robert G. McDonald, William Yoder, the TRIPS Team
Issue Date:July 2004
pp. 44-55
Post-RISC microprocessor designs must introduce new ISAs to address the challenges that modern CMOS technologies pose while also exploiting the massive levels of integration now possible. To meet these challenges, the TRIPS Team at the University of Texas ...
 
Exploiting microarchitectural redundancy for defect tolerance
Found in: 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)
By Premkishore Shivakumar,Stephen W. Keckler,Charles R. Moore,Doug Burger
Issue Date:September 2012
pp. 35-42
The continued increase in microprocessor clock frequency that has come from advancements in fabrication technology and reductions in feature size, creates challenges in maintaining both manufacturing yield rates and long-term reliability of devices. Method...
 
Scalable Hardware Memory Disambiguation for High-ILP Processors
Found in: IEEE Micro
By Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler
Issue Date:November 2004
pp. 118-127
Power is a major problem for scaling the hardware needed to support memory disambiguation in future out-of-order architectures. In current machines, the traditional detection of memory ordering violations requires frequent associative searches of state pro...
 
Exploiting Microarchitectural Redundancy For Defect Tolerance
Found in: Computer Design, International Conference on
By Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger
Issue Date:October 2003
pp. 481
The continued increase in microprocessor clock frequency that has come from advancements in fabrication technology and reductions in feature size, creates challenges in maintaining both manufacturing yield rates and long-term reliability of devices. Method...
 
The Power PC 601 Microprocessor
Found in: IEEE Micro
By Michael K. Becker, Michael S. Allen, Charles R. Moore, John S. Muhich, David P. Tuttle
Issue Date:September 1993
pp. 54-68
<p>The PowerPC 601 microprocessor, the first of a family of processors based on the PowerPC architecture, is described. The general-purpose processor contains a 32-Kb cache and a superscalar machine organization that allows dispatch and execution of ...
 
The PowerPC alliance
Found in: Communications of the ACM
By Charles R. Moore, Russell C. Stanphill
Issue Date:January 1988
pp. 25-27
We consider here the importance of an overall systems viewpoint in avoiding computer-related risks. According to Webster's, a system is a regularly interacting or interdependent group of items forming a unified whole. In computer systems, one person's comp...
     
Character string manipulation in APL
Found in: Proceedings of the sixth international conference on APL (APL '74)
By Charles R. Moore
Issue Date:January 1974
pp. 349-353
Use of the NMSU EXECUTE enhancement at PCS (since September 1973) has opened the way to many new applications and programming techniques, Most of these applications have been in the area of packages where the user communicates indirectly with APL through a...
     
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