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Displaying 1-45 out of 45 total
Hierarchical modeling of Phase Change memory for reliable design
Found in: 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)
By Zihan Xu,Ketul B. Sutaria,Chengen Yang,Chaitali Chakrabarti,Yu Cao
Issue Date:September 2012
pp. 115-120
As CMOS based memory devices near their end, memory technologies, such as Phase Change Random Access Memory (PRAM), have emerged as viable alternatives. This work develops a hierarchical modeling framework that connects the unique device physics of PRAM wi...
 
LA-LRU: A Latency-Aware Replacement Policy for Variation Tolerant Caches
Found in: VLSI Design, International Conference on
By Aarul Jain, Aviral Shrivastava, Chaitali Chakrabarti
Issue Date:January 2011
pp. 298-303
Parameter variations in deep sub-micron integrated circuits cause chip characteristics to deviate during semiconductor fabrication process. These variations are dominant in memory systems such as caches and the delay spread due to process variation impacts...
 
Mobile Supercomputers for the Next-Generation Cell Phone
Found in: Computer
By Mark Woh, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti
Issue Date:January 2010
pp. 81-85
AnySP demonstrates that power efficiency can be achieved on a fully programmable processor in the context of a future mobile terminal supporting 4G wireless and high-definition video coding.
 
Low power robust signal processing
Found in: Low Power Electronics and Design, International Symposium on
By Veera Papirla, Aarul Jain, Chaitali Chakrabarti
Issue Date:August 2009
pp. 303-306
Voltage scaling has proven to be very effective in reducing the power consumption of digital systems. However, voltage overscaling, ie., reducing the voltage below the critical voltage, introduces errors which have to be compensated by additional computati...
 
From SODA to scotch: The evolution of a wireless baseband processor
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Mark Woh, Yuan Lin, Sangwon Seo, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, Richard Bruce, Danny Kershaw, Alastair Reid, Mladen Wilder, Krisztian Flautner
Issue Date:November 2008
pp. 152-163
With the multitude of existing and upcoming wireless standards, it is becoming increasingly difficult for hardware-only baseband processing solutions to adapt to the rapidly changing wireless communication landscape. Software Defined Radio (SDR) promises t...
 
Extending the lifetime of media recorders constrained by battery and flash memory size
Found in: Low Power Electronics and Design, International Symposium on
By Younghyun Kim, Youngjin Cho, Naehyuck Chang, Chaitali Chakrabarti, Nam Ik Cho
Issue Date:August 2008
pp. 159-164
The lifetime of a stand-alone media recorder is a function of both the battery size and flash memory size. In this paper, we present a power management framework for media recorders that significantly enhances their lifetime while minimizing the flash memo...
 
Energy management of DVS-DPM enabled embedded systems powered by fuel cell-battery hybrid source
Found in: Low Power Electronics and Design, International Symposium on
By Jianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang
Issue Date:August 2007
pp. 322-327
Dynamic voltage scaling (DVS) and dynamic power management (DPM) are the two main techniques for reducing the energy consumption of embedded systems. The effectiveness of both DVS and DPMneeds to be considered in the development of an energy management pol...
 
Throughput of multi-core processors under thermal constraints
Found in: Low Power Electronics and Design, International Symposium on
By Ravishankar Rao, Sarma Vrudhula, Chaitali Chakrabarti
Issue Date:August 2007
pp. 201-206
We analyze the effect of thermal constraints on the performance and power of multi-core processors. We propose system-level power and thermal models, and derive expressions for (a) the maximum number of cores that can be activated, with and without throttl...
 
SODA: A Low-power Architecture For Software Radio
Found in: Computer Architecture, International Symposium on
By Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, Krisztian Flautner
Issue Date:June 2006
pp. 89-101
The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a minimum. These implementations are time consuming to design and difficult to ...
 
Mobile Supercomputers
Found in: Computer
By Todd Austin, David Blaauw, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, Wayne Wolf
Issue Date:May 2004
pp. 81-83
Current trends in computer architecture and power cannot meet the demands of mobile supercomputing. Significant innovation is required.
 
Battery-Conscious Task Sequencing for Portable Devices Including Voltage/Clock Scaling
Found in: Design Automation Conference
By Daler Rakhmatov, Sarma Vrudhula, Chaitali Chakrabarti
Issue Date:June 2002
pp. 189
Operation of battery-powered portable systems can no longer be sustained once a battery becomes discharged. Maximization of the battery lifetime is a difficult task due to nonlinearity of battery behavior that depends on the characteristics of the system l...
 
Relating Data Characteristics to Transition Activity in High-Level Static CMOS Design
Found in: VLSI Design, International Conference on
By Russell Henning, Chaitali Chakrabarti
Issue Date:January 2000
pp. 38
Significant power reduction can be obtained in the datapath of a CMOS VLSI circuit if data characteristics are carefully exploited. An improved approach that achieves such reduction by using a new model relating important data characteristics to the transi...
 
Memory Exploration for Low Power, Embedded Systems
Found in: Design Automation Conference
By Wen-Tsong Shiue, Chaitali Chakrabarti
Issue Date:June 1999
pp. 140-145
In embedded system design, the designer has to choose an on-chip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory exploration strategy based on three performance metrics, namely, cache size...
 
Sonic Millip3De: A massively parallel 3D-stacked accelerator for 3D ultrasound
Found in: 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)
By Richard Sampson,Ming Yang,Siyuan Wei,Chaitali Chakrabarti,Thomas F. Wenisch
Issue Date:February 2013
pp. 318-329
Three-dimensional (3D) ultrasound is becoming common for non-invasive medical imaging because of its high accuracy, safety, and ease of use. Unlike other modalities, ultrasound transducers require little power, which makes hand-held imaging platforms possi...
 
AnySP: Anytime Anywhere Anyway Signal Processing
Found in: IEEE Micro
By Mark Woh, Sangwon Seo, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, KrisztiƔn Flautner
Issue Date:January 2010
pp. 81-91
<p>Looking forward, the computation requirements of mobile devices will increase by one to two orders of magnitude, but their power requirements will remain stringent to ensure reasonable battery lifetimes. Scaling existing approaches won't suffice; ...
 
SODA: A High-Performance DSP Architecture for Software-Defined Radio
Found in: IEEE Micro
By Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, KrisztiƔn Flautner
Issue Date:January 2007
pp. 114-123
Software-defined radio (SDR) belongs to an emerging class of applications with the processing requirements of a supercomputer but the power constraints of a mobile terminal. The authors developed the Signal-Processing On-Demand Architecture (SODA), a fully...
 
High-Level Design Synthesis of a Low Power, VLIW Processor for the IS-54 VSELP Speech Encoder
Found in: Computer Design, International Conference on
By Russell E. Henning, Chaitali Chakrabarti
Issue Date:October 1997
pp. 571
General purpose DSPs typically used to implement speech coders in digital cellular phones do not allow enough exploitation of the speech coding algorithm itself for power reduction. In this paper, high-level design synthesis of a low power, VLIW (very long...
 
A new Viterbi decoder design for code rate k/n
Found in: Acoustics, Speech, and Signal Processing, IEEE International Conference on
By Hsiang-Ling Li, Chaitali Chakrabarti
Issue Date:May 1995
pp. 2743-2746
A novel VLSI architecture is proposed for implementing a long constraint length Viterbi decoder (VD) for code rate k/n. This architecture is based on the encoding structure where k input bits are shifted into k shift registers in each cycle. The architectu...
 
A survey of architectures for the discrete and continuous wavelet transforms
Found in: Acoustics, Speech, and Signal Processing, IEEE International Conference on
By Chaitali Chakrabarti, Mohan Vishwanath, R.M. Owens
Issue Date:May 1995
pp. 2849-2852
Wavelet transforms have proven to be useful tools for several applications, including signal analysis, signal coding, and image compression. This paper surveys the VLSI architectures that have been proposed for computing the discrete and continuous wavelet...
 
Sonic Millip3De: An Architecture for Handheld 3D Ultrasound
Found in: IEEE Micro
By Richard Sampson,Ming Yang,Siyuan Wei,Chaitali Chakrabarti,Thomas F. Wenisch
Issue Date:May 2014
pp. 100-108
3D ultrasound is becoming common for noninvasive medical imaging because of its high accuracy, safety, and ease of use. Unlike other modalities, ultrasound transducers require little power, which makes handheld imaging platforms possible, and several low-r...
 
WiBench: An open source kernel suite for benchmarking wireless systems
Found in: 2013 IEEE International Symposium on Workload Characterization (IISWC)
By Qi Zheng,Yajing Chen,Ronald Dreslinski,Chaitali Chakrabarti,Achilleas Anastasopoulos,Scott Mahlke,Trevor Mudge
Issue Date:September 2013
pp. 123-132
The rapid growth in the number of mobile devices and the higher data rate requirements of mobile subscribers have made wireless signal processing a key driving application of mobile computing technology. To design better mobile platforms and the supporting...
   
Voltage Scaling for Energy Minimization with QoS Constraints
Found in: Computer Design, International Conference on
By Ali Manzak, Chaitali Chakrabarti
Issue Date:September 2001
pp. 0438
Abstract: In this paper we propose variable voltage scheduling algorithms that minimize energy while satisfying the quality of service requirements. We consider the case when multiple applications are running on a single processor equipped with a limited s...
 
Address Code Generation for Digital Signal Processors
Found in: Design Automation Conference
By Chaitali Chakrabarti, Sathishkumar Udayanarayanan
Issue Date:June 2001
pp. 353-358
In this paper we propose a procedure to generate code with minimum number of addressing instructions. We analyze different methods of generating addressing code for scalar variables and quantify the improvements due to optimizations such as offset assignme...
 
Exploring DRAM organizations for energy-efficient and resilient exascale memories
Found in: Proceedings of SC13: International Conference for High Performance Computing, Networking, Storage and Analysis (SC '13)
By Bharan Giridhar, Chaitali Chakrabarti, David Blaauw, Deepankar Duggal, Hsing Min Chen, Michael Cieslak, Betina Hold, Robert Patti, Ronald Dreslinski, Trevor Mudge
Issue Date:November 2013
pp. 1-12
The power target for exascale supercomputing is 20MW, with about 30% budgeted for the memory subsystem. Commodity DRAMs will not satisfy this requirement. Additionally, the large number of memory chips (>10M) required will result in crippling failure ra...
     
Diet SODA: a power-efficient processor for digital cameras
Found in: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design (ISLPED '10)
By Chaitali Chakrabarti, Mark Woh, Ronald G. Dreslinski, Sangwon Seo, Scott Mahlke, Trevor Mudge
Issue Date:August 2010
pp. 79-84
Power has become the most critical design constraint for embedded handheld devices. This paper proposes a power-efficient SIMD architecture, referred to as Diet SODA, for DSP applications. The key design idea is to apply near-threshold operation on a singl...
     
Low power robust signal processing
Found in: Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design (ISLPED '09)
By Aarul Jain, Chaitali Chakrabarti, Veera Papirla
Issue Date:August 2009
pp. 1-2
Voltage scaling has proven to be very effective in reducing the power consumption of digital systems. However, voltage overscaling, ie., reducing the voltage below the critical voltage, introduces errors which have to be compensated by additional computati...
     
Energy-aware error control coding for Flash memories
Found in: Proceedings of the 46th Annual Design Automation Conference (DAC '09)
By Chaitali Chakrabarti, Veera Papirla
Issue Date:July 2009
pp. 658-663
The use of Flash memories in portable embedded systems is ever increasing. This is because of the multi-level storage capability that makes them excellent candidates for high density memory devices. However, cost of writing or programming Flash memories is...
     
AnySP: anytime anywhere anyway signal processing
Found in: Proceedings of the 36th annual international symposium on Computer architecture (ISCA '09)
By Chaitali Chakrabarti, Krisztian Flautner, Mark Woh, Sangwon Seo, Scott Mahlke, Trevor Mudge
Issue Date:June 2009
pp. 70-73
In the past decade, the proliferation of mobile devices has increased at a spectacular rate. There are now more than 3.3 billion active cell phones in the world-a device that we now all depend on in our daily lives. The current generation of devices employ...
     
Extending the lifetime of media recorders constrained by battery and flash memory size
Found in: Proceeding of the thirteenth international symposium on Low power electronics and design (ISLPED '08)
By Chaitali Chakrabarti, Naehyuck Chang, Nam Ik Cho, Younghyun Kim, Youngjin Cho
Issue Date:August 2008
pp. 383-384
The lifetime of a stand-alone media recorder is a function of both the battery size and flash memory size. In this paper, we present a power management framework for media recorders that significantly enhances their lifetime while minimizing the flash memo...
     
Energy-efficient dynamic task scheduling algorithms for DVS systems
Found in: ACM Transactions on Embedded Computing Systems (TECS)
By Chaitali Chakrabarti
Issue Date:February 2008
pp. 1-25
Dynamic voltage scaling (DVS) is a well-known low-power design technique that reduces the processor energy by slowing down the DVS processor and stretching the task execution time. However, in a DVS system consisting of a DVS processor and multiple devices...
     
A fuel-cell-battery hybrid for portable embedded systems
Found in: ACM Transactions on Design Automation of Electronic Systems (TODAES)
By Chaitali Chakrabarti
Issue Date:January 2008
pp. 1-34
This article presents our work on the development of a fuel cell (FC) and battery hybrid (FC-Bh) system for use in portable microelectronic systems. We describe the design and control of the hybrid system, as well as a dynamic power management (DPM)-based ...
     
Energy management of DVS-DPM enabled embedded systems powered by fuel cell-battery hybrid source
Found in: Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)
By Chaitali Chakrabarti, Jianli Zhuo, Naehyuck Chang
Issue Date:August 2007
pp. 322-327
Dynamic voltage scaling (DVS) and dynamic power management (DPM) are the two main techniques for reducing the energy consumption of embedded systems. The effectiveness of both DVS and DPMneeds to be considered in the development of an energy management pol...
     
Throughput of multi-core processors under thermal constraints
Found in: Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)
By Chaitali Chakrabarti, Ravishankar Rao, Sarma Vrudhula
Issue Date:August 2007
pp. 201-206
We analyze the effect of thermal constraints on the performance and power of multi-core processors. We propose system-level power and thermal models, and derive expressions for (a) the maximum number of cores that can be activated, with and without throttl...
     
Dynamic power management with hybrid power sources
Found in: Proceedings of the 44th annual conference on Design automation (DAC '07)
By Chaitali Chakrabarti, Jianli Zhuo, Kyungsoo Lee, Naehyuck Chang
Issue Date:June 2007
pp. 871-876
DPM (Dynamic Power Management) is an effective technique for reducing the energy consumption of embedded systems that is based on migrating to a low power state when possible. While conventional DPM minimizes the energy consumption of the embedded system, ...
     
Maximizing the lifetime of embedded systems powered by fuel cell-battery hybrids
Found in: Proceedings of the 2006 international symposium on Low power electronics and design (ISLPED '06)
By Chaitali Chakrabarti, Jianli Zhuo, Naehyuck Chang, Sarma Vrudhula
Issue Date:October 2006
pp. 424-429
Fuel cells are a viable alternative power source for portable applications. They have higher energy density than traditional Li-ion batteries and can achieve longer lifetime for the same weight or volume. However, because of their limited power density, th...
     
An optimal analytical solution for processor speed control with thermal constraints
Found in: Proceedings of the 2006 international symposium on Low power electronics and design (ISLPED '06)
By Chaitali Chakrabarti, Naehyuck Chang, Ravishankar Rao, Sarma Vrudhula
Issue Date:October 2006
pp. 292-297
As semiconductor manufacturing technology scales to smaller device sizes, the power consumption of clocked digital ICs begins to increase. Dynamic voltage and frequency scaling (DVFS) is a well-known technique for conserving energy. Recently, it has also b...
     
Reducing idle mode power in software defined radio terminals
Found in: Proceedings of the 2006 international symposium on Low power electronics and design (ISLPED '06)
By Chaitali Chakrabarti, Hyunseok Lee, Trevor Mudge
Issue Date:October 2006
pp. 101-106
In this paper, we propose a processor which is optimized for idle mode operation of a software defined radio (SDR) terminal. Since a SDR terminal spends most of its time in the idle mode, reducing the power consumption in this mode directly translates to l...
     
High-level power management of embedded systems with application-specific energy cost functions
Found in: Proceedings of the 43rd annual conference on Design automation (DAC '06)
By Chaitali Chakrabarti, Naehyuck Chang, Sarma Vrudhula, Youngjin Cho
Issue Date:July 2006
pp. 568-573
Most existing dynamic voltage scaling (DVS) schemes for multiple tasks assume an energy cost function (energy consumption versus execution time) that is independent of the task characteristics. In practice the actual energy cost functions vary significantl...
     
Extending the lifetime of fuel cell based hybrid systems
Found in: Proceedings of the 43rd annual conference on Design automation (DAC '06)
By Chaitali Chakrabarti, Jianli Zhuo, Naehyuck Chang, Sarma Vrudhula
Issue Date:July 2006
pp. 562-567
Fuel cells are clean power sources that have much higher energy densities and lifetimes compared to batteries. However, fuel cells have limited load following capabilities and cannot be efficiently utilized if used in isolation. In this work, we consider a...
     
System-level energy-efficient dynamic task scheduling
Found in: Proceedings of the 42nd annual conference on Design automation (DAC '05)
By Chaitali Chakrabarti, Jianli Zhuo
Issue Date:June 2005
pp. 628-631
Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor energy by slowing down the DVS processor and stretching the task execution time. But in a DVS system consisting of a DVS processor and multiple devices, slo...
     
Battery-conscious task sequencing for portable devices including voltage/clock scaling
Found in: Proceedings of the 39th conference on Design automation (DAC '02)
By Chaitali Chakrabarti, Daler Rakhmatov, Sarma Vrudhula
Issue Date:June 2002
pp. 189-194
Operation of battery-powered portable systems can no longer be sustained once a battery becomes discharged. Maximization of the battery lifetime is a difficult task due to nonlinearity of battery behavior that depends on the characteristics of the system l...
     
Variable voltage task scheduling algorithms for minimizing energy
Found in: Proceedings of the 2001 international symposium on Low power electronics and design (ISLPED '01)
By Ali Manzak, Chaitali Chakrabarti
Issue Date:August 2001
pp. 279-282
Wireless communications and more specifically, the fast growing penetration of cellular phones and cellular infrastructure are the major drivers for the development of new programmable Digital Signal Processors (DSPs). In this tutorial, an overview will be...
     
Address code generation for digital signal processors
Found in: Proceedings of the 38th conference on Design automation (DAC '01)
By Chaitali Chakrabarti, Sathishkumar Udayanarayanan
Issue Date:June 2001
pp. 353-358
In this paper we propose a procedure to generate code with minimum number of addressing instructions. We analyze different methods of generating addressing code for scalar variables and quantify the improvements due to optimizations such as offset assignme...
     
Energy-efficient code generation for DSP56000 family (poster session)
Found in: Proceedings of the 2000 international symposium on Low power electronics and design (ISLPED '00)
By Chaitali Chakrabarti, Sathishkumar Udayanarayanan
Issue Date:July 2000
pp. 247-249
This paper presents a procedure to generate energy-efficient code for the Motorola DSP56K processor based on increasing the packing efficiency and minimizing the number of address instructions. The key features are a novel scheduling algorithm that reduces...
     
Memory exploration for low power, embedded systems
Found in: Proceedings of the 36th ACM/IEEE conference on Design automation conference (DAC '99)
By Chaitali Chakrabarti, Wen-Tsong Shiue
Issue Date:June 1999
pp. 140-145
We present the SpecSyn system-level design environment supp orting the sp ecify-explor e-refine (SER) designparadigm. This thr ee-step appr oach includes precise specification of system functionality, rapid explor ation of numerous system-level design opti...
     
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