Search For:

Displaying 1-12 out of 12 total
Transient Fault Emulation of Hardened Circuits in FPGA Platforms
Found in: On-Line Testing Symposium, IEEE International
By Mario García-Valderas, Celia López-Ongil, Marta Portela-García, Luis Entrena-Arrontes
Issue Date:July 2004
pp. 109
Very deep submicron and nanometer technologies are emphasizing soft errors as an important issue in the challenges of modern electronic systems. Hardened circuits are currently required in many applications where Fault Tolerance (FT) was not a requirement ...
 
Robust cryptographic ciphers with on-line statistical properties validation
Found in: On-Line Testing Symposium, IEEE International
By Anna Vaskova, Celia Lopez-Ongil, Alejandro Jimenez-Horas, Enrique San Millan, Luis Entrena
Issue Date:July 2010
pp. 208-210
A new solution is presented for fast measuring of randomness properties of cryptographic algorithms. Statistical Tests from NIST are hardware implemented in order to enable an on-line detection of intentional attacks in cryptographic ciphers. The small are...
 
Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers
Found in: On-Line Testing Symposium, IEEE International
By Alejandro Jimenez-Horas, Enrique San Millan, Celia Lopez-Ongil, Marta Portela-Garcia, Mario Garcia-Valderas, Luis Entrena
Issue Date:June 2009
pp. 203-205
Latest mitigation techniques proposed at register-transfer level for dependable cryptosystems deal with time redundancy in an active on-line error-detection scheme. Round-based block ciphers are very likely to be hardened with these techniques. Although go...
 
Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard
Found in: On-Line Testing Symposium, IEEE International
By Celia López-Ongil, Alejandro Jiménez-Horas, Marta Portela-García, Mario García-Valderas, Enrique San Millán, Luis Entrena
Issue Date:July 2008
pp. 167-168
Encryption algorithms could suffer fault injection attacks in order to obtain the secret key. In this paper, a specific protection for any round-based encryption algorithm is presented, analyzed and tested. It is providing a high degree of robustness toget...
 
SET Emulation Under a Quantized Delay Model
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Mario García Valderas, Raúl Fernández Cardenal, Celia López Ongil, Marta Portela García, Luis Entrena
Issue Date:September 2007
pp. 68-78
Single Event Transient (SET) fault analysis is usually performed trough digital simulation at the gate level. However, this method cannot be used for large fault injection campaigns, since gate level simulation is quite slow. In this paper, we propose an a...
 
A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors
Found in: On-Line Testing Symposium, IEEE International
By Marta Portela-Garcia, Celia López-Ongil, Mario Garcia-Valderas, Luis Entrena
Issue Date:July 2007
pp. 101-106
Processors are very common components in current digital systems and to assess their reliability is an essential task during the design process. In this paper a new fault injection solution to measure SEU sensitivity in processors is presented. It consists...
 
Emulation-based Fault Injection in Circuits with Embedded Memories
Found in: On-Line Testing Symposium, IEEE International
By Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena
Issue Date:July 2006
pp. 183-184
FPGA emulation has proven to be a performance effective method to analyse the behaviour of digital circuits in the presence of soft errors due to SEU effects. In particular, the recently developed Autonomous Emulation techniques allow the classification of...
   
Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading
Found in: On-Line Testing Symposium, IEEE International
By Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes
Issue Date:July 2005
pp. 43-48
Very deep submicron and nanometer technologies have increased notably integrated circuit (IC) sensitiveness to radiation. Soft errors are currently appearing into ICs working at earth surface. Therefore, hardened circuits are currently required in many app...
 
Techniques for Fast Transient Fault Grading Based on Autonomous Emulation
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes
Issue Date:March 2005
pp. 308-309
Very deep submicron and nanometer technologies have increased notably integrated circuit (IC) sensitiveness to radiation. Soft errors are currently appearing into ICs working at earth surface. Hardened circuits are currently required in many applications w...
   
Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures
Found in: IEEE Transactions on Dependable and Secure Computing
By Marta Portela-García,Celia López-Ongil,Mario García Valderas,Luis Entrena
Issue Date:March 2011
pp. 308-314
In this paper, a new fault injection approach to measure SEU sensitivity in COTS microprocessors is presented. It consists in a hardware-implemented module that performs fault injection through the available JTAG-based On-Chip Debugger (OCD). This approach...
 
In-depth analysis of digital circuits against soft errors for selective hardening
Found in: On-Line Testing Symposium, IEEE International
By Mario Garcia-Valderas, Marta Portela-Garcia, Celia Lopez-Ongil, Luis Entrena
Issue Date:June 2009
pp. 144-149
SEU effects are a main concern in an increasing number of applications. Selective hardening in early design stages is intended to design a robust circuit in a fast and cost-efficient way. In this paper, a method to performing selective hardening in digital...
 
Briefing power/reliability optimization in embedded software design
Found in: On-Line Testing Symposium, IEEE International
By Fabian Vargas, Claudia A. Rocha, Bernardo Pianta, Marta Portela Garcia, Celia Lopez Ongil, Mario Garcia Valderas, Luis Entrena
Issue Date:June 2009
pp. 185-186
We propose an approach<sup>1</sup> to optimize the number of checkpoints to be inserted along with an application code. The approach is based on a profiling process that analyzes the application code control-flow graph to find the best trade-of...
 
 1