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Displaying 1-7 out of 7 total
Characterizing the latency hiding ability of GPUs
Found in: 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
By Shin-Ying Lee,Carole-Jean Wu
Issue Date:March 2014
pp. 145-146
This paper demonstrates a latency profiling approach to characterize and evaluate for the latency-hiding capability of modern GPU architectures. We find that the fast context-switching and massive multi-threading architecture can effectively hide much of t...
   
Performance, energy characterizations and architectural implications of an emerging mobile platform benchmark suite - MobileBench
Found in: 2013 IEEE International Symposium on Workload Characterization (IISWC)
By Dhinakaran Pandiyan,Shin-Ying Lee,Carole-Jean Wu
Issue Date:September 2013
pp. 133-142
In this paper, we explore key microarchitectural features of mobile computing platforms that are crucial to the performance of smart phone applications. We create and use a selection of representative smart phone applications, which we call MobileBench tha...
   
Architectural Thermal Energy Harvesting Opportunities for Sustainable Computing
Found in: IEEE Computer Architecture Letters
By Carole-Jean Wu
Issue Date:June 2013
pp. 1
Increased power dissipation in computing devices has led to a sharp rise in thermal hotspots, creating thermal runaway. To reduce the additional power requirement caused by increased temperature, current approaches seek to apply cooling mechanisms to aggre...
 
Characterization and dynamic mitigation of intra-application cache interference
Found in: Performance Analysis of Systems and Software, IEEE International Symmposium on
By Carole-Jean Wu, Margaret Martonosi
Issue Date:April 2011
pp. 2-11
Given the emerging dominance of CMPs, an important research problem concerns application memory performance in the face of deep memory hierarchies, where one or more caches are shared by several cores. In current systems, many factors can cause interferenc...
 
PACMan: prefetch-aware cache management for high performance caching
Found in: Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-44 '11)
By Aamer Jaleel, Joel Emer, Carole-Jean Wu, Margaret Martonosi, Simon C. Steely
Issue Date:December 2011
pp. 442-453
Hardware prefetching and last-level cache (LLC) management are two independent mechanisms to mitigate the growing latency to memory. However, the interaction between LLC management and hardware prefetching has received very little attention. This paper cha...
     
SHiP: signature-based hit predictor for high performance caching
Found in: Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-44 '11)
By Aamer Jaleel, Carole-Jean Wu, Margaret Martonosi, Simon C. Steely, Joel Emer, Will Hasenplaugh
Issue Date:December 2011
pp. 430-441
The shared last-level caches in CMPs play an important role in improving application performance and reducing off-chip memory bandwidth requirements. In order to use LLCs more efficiently, recent research has shown that changing the re-reference prediction...
     
Adaptive timekeeping replacement: Fine-grained capacity management for shared CMP caches
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By Carole-Jean Wu, Margaret Martonosi
Issue Date:April 2011
pp. 1-26
In chip multiprocessors (CMPs), several high-performance cores typically compete for capacity in a shared last-level cache. This causes degraded and unpredictable memory performance for multiprogrammed and parallel workloads. In response, recent schemes ap...
     
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