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Displaying 1-4 out of 4 total
An I-IP based approach for the monitoring of NBTI effects in SoCs
Found in: On-Line Testing Symposium, IEEE International
By C. Guardiani, A. Shibkov, A. Brambilla, G. Storti Gajani, D. Appello, F. Piazza, P. Bernardi
Issue Date:June 2009
pp. 15-20
In this paper we present a design for reliability methodology, with the goal of reducing the impact of transistor V<inf>TH</inf> degradation due for example to phenomena such as NBTI. It uses infrastructure IPs (I-IPs) featuring a self compensa...
Analog IP Testing: Diagnosis and Optimization
Found in: Design, Automation and Test in Europe Conference and Exhibition
By C. Guardiani, P. McNamara, L. Daldoss, S. Saxena, S. Zanella, W. Xiang, S. Liu
Issue Date:March 2002
pp. 0192
In this paper, we present an innovative methodology to estimate and improve the quality of analog and mixed-signal circuit testing. We first detect and reduce the redundancy in the electrical test measurements (e-tests), then we identify the e-test accepta...
Found in: 2007 10th Design, Automation and Test in Europe Conference and Exhibition
By R. Aitken,A. Domic,C. Guardiani,P. Magarshack,D. Pattullo,J. Sawicki
Issue Date:April 2007
pp. 1-4
Everybody agrees that curing DFM/DFY issues is of paramount importance at 65 nanometers and beyond. Unfortunately, there is disagreement about how and when to cure them.
Yield-aware placement optimization
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '07)
By C. Guardiani, F. Fummi, M. Bertoletti, N. Dragone, P. Azzoni, W. Vendraminetto
Issue Date:April 2007
pp. 1232-1237
In this paper we describe a methodology addressing the issue of avoiding yield hazardous cell abutments during placement. This is made possible by accurate characterization of the yield penalty associated with particular cell-to-cell interactions. Of cours...