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Displaying 1-14 out of 14 total
Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip
Found in: IEEE Transactions on Computers
By Hyungjun Kim,Boris Grot,Paul V. Gratz,Daniel A. Jimenez
Issue Date:March 2014
pp. 543-556
As processor chips become increasingly parallel, an efficient communication substrate is critical for meeting performance and energy targets. In this work, we target the root cause of network energy consumption through techniques that reduce link and route...
NOC-Out: Microarchitecting a Scale-Out Processor
Found in: 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
By Pejman Lotfi-Kamran,Boris Grot,Babak Falsafi
Issue Date:December 2012
pp. 177-187
Scale-out server workloads benefit from many-core processor organizations that enable high throughput thanks to abundant request-level parallelism. A key characteristic of these workloads is the large instruction footprint that exceeds the capacity of priv...
Optimizing Data-Center TCO with Scale-Out Processors
Found in: IEEE Micro
By Boris Grot,Damien Hardy,Pejman Lotfi-Kamran,Babak Falsafi,Chrysostomos Nicopoulos,Yiannakis Sazeides
Issue Date:September 2012
pp. 52-63
Performance and total cost of ownership (TCO) are key optimization metrics in large-scale data centers. According to these metrics, data centers designed with conventional server processors are inefficient. Recently introduced processors based on low-power...
CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers
Found in: Networks-on-Chip, International Symposium on
By Stavros Volos,Ciprian Seiculescu,Boris Grot,Naser Khosro Pour,Babak Falsafi,Giovanni De Micheli
Issue Date:May 2012
pp. 67-74
Many core chips are emerging as the architecture of choice to provide power efficiency and improve performance, while riding Moore's Law. In these architectures, on-chip inter-connects play a pivotal role in ensuring power and performance scalability. As s...
Big Data [Guest editors' introduction]
Found in: IEEE Micro
By Babak Falsafi,Boris Grot
Issue Date:July 2014
pp. 4-5
This introduction to the special issue discusses the opportunities and challenges in system design presented by big data and gives an overview of the articles in this issue.
FADE: A programmable filtering accelerator for instruction-grain monitoring
Found in: 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
By Sotiria Fytraki,Evangelos Vlachos,Onur Kocberber,Babak Falsafi,Boris Grot
Issue Date:February 2014
pp. 108-119
Instruction-grain monitoring is a powerful approach that enables a wide spectrum of bug-finding tools. As existing software approaches incur prohibitive runtime overhead, researchers have focused on hardware support for instruction-grain monitoring. A recu...
Scale-out NUMA
Found in: Proceedings of the 19th international conference on Architectural support for programming languages and operating systems (ASPLOS '14)
By Alexandros Daglis, Babak Falsafi, Boris Grot, Edouard Bugnion, Stanko Novakovic
Issue Date:March 2014
pp. 3-18
Emerging datacenter applications operate on vast datasets that are kept in DRAM to minimize latency. The large number of servers needed to accommodate this massive memory footprint requires frequent server-to-server communication in applications such as ke...
Meet the walkers: accelerating index traversals for in-memory databases
Found in: Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46)
By Boris Grot, Kevin Lim, Onur Kocberber, Parthasarathy Ranganathan, Babak Falsafi, Javier Picorel
Issue Date:December 2013
pp. 468-479
The explosive growth in digital data and its growing role in real-time decision support motivate the design of high-performance database management systems (DBMSs). Meanwhile, slowdown in supply voltage scaling has stymied improvements in core performance ...
SHIFT: shared history instruction fetch for lean-core server processors
Found in: Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46)
By Boris Grot, Babak Falsafi, Cansu Kaynak
Issue Date:December 2013
pp. 272-283
In server workloads, large instruction working sets result in high L1 instruction cache miss rates. Fast access requirements preclude large instruction caches that can accommodate the deep software stacks prevalent in server applications. Prefetching has b...
Scale-out processors
Found in: Proceedings of the 39th Annual International Symposium on Computer Architecture (ISCA '12)
By Almutaz Adileh, Babak Falsafi, Boris Grot, Djordje Jevdjic, Emre Ozer, Javier Picorel, Michael Ferdman, Onur Kocberber, Pejman Lotfi-Kamran, Sachin Idgunji, Stavros Volos
Issue Date:June 2012
pp. 500-511
Scale-out datacenters mandate high per-server throughput to get the maximum benefit from the large TCO investment. Emerging applications (e.g., data serving and web search) that run in these datacenters operate on vast datasets that are not accommodated by...
Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees
Found in: Proceeding of the 38th annual international symposium on Computer architecture (ISCA '11)
By Boris Grot, Joel Hestness, Onur Mutlu, Stephen W. Keckler
Issue Date:June 2011
pp. 401-412
Today's chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specialized accelerators are anticipated in the near future. In this paper, we propos...
Netrace: dependency-driven trace-based network-on-chip simulation
Found in: Proceedings of the Third International Workshop on Network on Chip Architectures (NoCArc '10)
By Boris Grot, Joel Hestness, Stephen W. Keckler
Issue Date:December 2010
pp. 31-36
Chip multiprocessors (CMPs) and systems-on-chip (SOCs) are expected to grow in core count from, a few today to hundreds or more. Since efficient on-chip communication is a primary factor in the performance of large core-count systems, the research communit...
Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip
Found in: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (Micro-42)
By Boris Grot, Onur Mutlu, Stephen W. Keckler
Issue Date:December 2009
pp. 268-279
Future many-core chip multiprocessors (CMPs) and systems-on-a-chip (SOCs) will have numerous processing elements executing multiple applications concurrently. These applications and their respective threads will interfere at the on-chip network level and c...
Segment gating for static energy reduction in Networks-on-Chip
Found in: Proceedings of the 2nd International Workshop on Network on Chip Architectures (NoCArc '09)
By Boris Grot, Kyle C. Hale, Stephen W. Keckler
Issue Date:December 2009
pp. 57-62
Chip multiprocessors (CMPs) have emerged as a primary vehicle for overcoming the limitations of uniprocessor scaling, with power constraints now representing a key factor of CMP design. Recent studies have shown that the on-chip interconnection network (NO...