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Displaying 1-50 out of 57 total
Reservation-Based Packet Bufferswith Deterministic Packet Departures
Found in: IEEE Transactions on Parallel and Distributed Systems
By Hao Wang,Bill Lin
Issue Date:May 2014
pp. 1297-1305
High-performance routers need to temporarily store a large number of packets in response to congestion. DRAM is typically needed to implement large packet buffers, but the worst-case random access latencies of DRAM devices are too slow to match the bandwid...
 
Robust Statistics Counter Arrays with Interleaved Memories
Found in: IEEE Transactions on Parallel and Distributed Systems
By Hao Wang,Bill Lin,Jun Jim Xu
Issue Date:September 2013
pp. 1894-1907
Statistics counters are essential in network measurement on tracking various network statistics and implementing various network counting sketches. For such applications it is crucial to maintain a large number of statistics counters at very high speeds. O...
 
Randomized Throughput-Optimal Oblivious Routing for Torus Networks
Found in: IEEE Transactions on Computers
By Rohit Sunkam Ramanujam,Bill Lin
Issue Date:March 2013
pp. 561-574
In this paper, we study the problem of optimal oblivious routing for 1D and 2D torus networks. We introduce a new closed-form oblivious routing algorithm called W2TURN that is worst-case throughput optimal for 2D torus networks. W2TURN is based on a weight...
 
Robust Pipelined Memory System with Worst Case Performance Guarantee for Network Processing
Found in: IEEE Transactions on Computers
By Hao Wang,Haiquan Zhao,Bill Lin,Jun Xu
Issue Date:October 2012
pp. 1386-1400
Many network processing applications require wirespeed access to large data structures or a large amount of packet and flow-level data. Therefore, it is essential for the memory system of a router to be able to support both read and write accesses to such ...
 
Oblivious routing design for mesh networks to achieve a new worst-case throughput bound
Found in: 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)
By Guang Sun,Chia-Wei Chang,Bill Lin,Lieguang Zeng
Issue Date:September 2012
pp. 427-432
1/2 network capacity is often believed to be the limit of worst-case throughput for mesh networks. However, this paper provides a new worst-case throughput bound, which is higher than 1/2 network capacity, for odd radix two-dimensional mesh networks. In ad...
 
Per-flow Queue Scheduling with Pipelined Counting Priority Index
Found in: High-Performance Interconnects, Symposium on
By Hao Wang,Bill Lin
Issue Date:August 2011
pp. 19-26
For advanced per-flow service disciplines at high-speed network links, it is essential to maintain priority queues in sorted order. The scalable priority queue implementation requires managing a large number of queues at ever increasing line speeds. In thi...
 
Design of a High-Throughput Distributed Shared-Buffer NoC Router
Found in: Networks-on-Chip, International Symposium on
By Rohit Sunkam Ramanujam, Vassos Soteriou, Bill Lin, Li-Shiuan Peh
Issue Date:May 2010
pp. 69-78
Router microarchitecture plays a central role in the performance of an on-chip network (NoC). Buffers are needed in routers to house incoming flits which cannot be immediately forwarded due to contention. This buffering can be done at the inputs or the out...
 
The Taming of the Shrew: Mitigating Low-Rate TCP-Targeted Attack
Found in: Distributed Computing Systems, International Conference on
By Chia-Wei Chang, Seungjoon Lee, Bill Lin, Jia Wang
Issue Date:June 2009
pp. 137-144
A Shrew attack, which uses a low-rate burst carefully designed to exploit TCP's retransmission timeout mechanism, can throttle the bandwidth of a TCP flow in a stealthy manner. While such an attack can significantly degrade the performance of all TCP-based...
 
A High-Throughput Distributed Shared-Buffer NoC Router
Found in: IEEE Computer Architecture Letters
By Vassos Soteriou, Rohit Sunkam Ramanujam, Bill Lin, Li-Shiuan Peh
Issue Date:January 2009
pp. 21-24
Microarchitectural configurations of buffers in routers have a significant impact on the overall performance of an on-chip network (NoC). This buffering can be at the inputs or the outputs of a router, corresponding to an input-buffered router (IBR) or an ...
 
Weighted Random Routing on Torus Networks
Found in: IEEE Computer Architecture Letters
By Rohit Sunkam Ramanujam, Bill Lin
Issue Date:January 2009
pp. 1-4
In this paper, we introduce a new closed-form oblivious routing algorithm called W2TURN that is worst-case throughput optimal for 2D-torus networks. W2TURN is based on a weighted random selection of paths that contain at most two turns. In terms of average...
 
Randomized Partially-Minimal Routing on Three-Dimensional Mesh Networks
Found in: IEEE Computer Architecture Letters
By Rohit Sunkam Ramanujam, Bill Lin
Issue Date:July 2008
pp. 37-40
This letter presents a new oblivious routing algorithm for 3D mesh networks called Randomized Partially- Minimal (RPM) routing that provably achieves optimal worstcase throughput for 3D meshes when the network radix k is even and within a factor of 1/k2 of...
 
Fast Buffer Memory with Deterministic Packet Departures
Found in: High-Performance Interconnects, Symposium on
By Mayank Kabra, Siddhartha Saha, Bill Lin
Issue Date:August 2006
pp. 67-72
High-performance routers need to store temporarily a large number of packets in response to congestion. DRAM is typically used to implement the needed packet buffers, but DRAM devices are too slow to match the bandwidth requirements. To bridge the bandwidt...
 
A Scalable Switch for Service Guarantees
Found in: High-Performance Interconnects, Symposium on
By Bill Lin, Isaac Keslassy
Issue Date:August 2005
pp. 93-99
<p>Operators need routers to provide service guarantees such as guaranteed flow rates and fairness among flows, so as to support real-time traffic and traffic engineering. However, current centralized input-queued router architectures cannot scale to...
 
Compositional Software Synthesis of Communicating Processes
Found in: Computer Design, International Conference on
By Xiaohan Zhu, Bill Lin
Issue Date:October 1999
pp. 646
In this paper, we describe a new compositional software synthesis method for synthesizing concurrent software programs into ordinary C programs so that they can be executed on embedded processors without the need for a run-time multi-tasking operating syst...
 
Hardware Compilation for FPGA-based Configurable Computing Machines
Found in: Design Automation Conference
By Xiaohan Zhu, Bill Lin
Issue Date:June 1999
pp. 697-702
Configurable computing machines are an emerging class of hybrid architectures where a field programmable gate array (FPGA) component is tightly coupled to a general-purpose microprocessor core. In these architectures, the FPGA component complements the gen...
 
Software Synthesis of Process-based Concurrent Programs
Found in: Design Automation Conference
By Bill Lin
Issue Date:June 1998
pp. 502-505
We present a Petri net theoretic approach to the software synthesis problem that can synthesize ordinary C programs from process-based concurrent specifications without the need for a run-time multi-threading environment. The synthesized C programs can be ...
 
Efficient Verification using Generalized Partial Order Analysis
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Steven Vercauteren, Diederik Verkest, Gjalt de Jong, Bill Lin
Issue Date:February 1998
pp. 782
This paper presents a new formal method for the efficient verification of concurrent systems that are modeled using a safe Petri net representation. Our method generalizes upon partial-order methods to explore concurrently enabled conflicting paths simulta...
 
Efficient Compilation of Process-Based Concurrent Programs without Run-Time Scheduling
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Bill Lin
Issue Date:February 1998
pp. 211
Currently, run-time operating systems are widely used to implement concurrent embedded applications. This run-time approach to multi-tasking and inter-process communication can introduce significant overhead to execution times and memory requirements -- pr...
 
A System Design Methodology for Telecommunication Network Applications
Found in: Great Lakes Symposium on VLSI
By Julio Leao da Silva, Jr., Chantal Ykman-Couvreur, Bill Lin, Hugo de Man, Gjalt de Jong
Issue Date:March 1997
pp. 64
We describe a system design methodology, well-suited for telecom network applications. This methodology is being developed into a compiler called Matisse. The entry point for this methodology is a system specification model that is first compiled into an a...
 
Flow Graph Balancing for Minimizing the Required Memory Bandwidth
Found in: System Synthesis, International Symposium on
By Sven Wuytack, Francky Catthoor, Gjalt de Jong, Bill Lin, Hugo de Man
Issue Date:November 1996
pp. 127
In this paper we present the problem of flow graph balancing for minimizing the required memory bandwidth. Our goal is to minimize the required memory bandwidth within the given cycle budget by adding ordering constraints to the flow graph. This allows the...
 
Efficient Partial Enumeration for Timing Analysis of Asynchronous Systems
Found in: Design Automation Conference
By Eric Verlind, Gjalt de Jong, Bill Lin
Issue Date:June 1996
pp. 55-58
This paper presents an efficient method for the timing verification of concurrent systems, modeled as labeled Timed Petri nets. The verification problems we consider require us to analyze the system's reachable behaviors under the specified time delays. Ou...
 
A System Design Methodology for Software/Hardware Co-Development of Telecommunication Network Applications
Found in: Design Automation Conference
By Bill Lin
Issue Date:June 1996
pp. 672-677
In this paper, we describe a system design methodology for the concurrent development of hybrid software/hardware systems for telecom network applications. This methodology is based on the results of an investigation and evaluation of an actual industrial ...
 
A Strategy for Real-Time Kernel Support in Application-Specific HW/SW Embedded Architectures
Found in: Design Automation Conference
By Steven Vercauteren, Bill Lin, Hugo De Man
Issue Date:June 1996
pp. 678-683
Heterogeneous embedded multiprocessor architectures are becoming more prominent as a key design solution to today's microelectronics design problems. These application-specific architectures integrate multiple software programmable processors and dedicated...
 
Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications
Found in: Design Automation Conference
By Steven Vercauteren, Bill Lin, Hugo De Man
Issue Date:June 1996
pp. 521-526
Deep sub-micron processing technologies have enabled the implementation of new application-specificembeddedarchitecturesthat integrate multiple software programmable processors (e.g. DSPs, microcontrollers) and dedicated hardware components together onto a...
 
Embedded Architecture Co-Synthesis and System Integration
Found in: Hardware/Software Co-Design, International Workshop on
By Bill Lin, Steven Vercauteren, Hugo de Man Imec
Issue Date:March 1996
pp. 2
No summary available.
 
Control Resynthesis for Control-Dominated Asynchronous Designs
Found in: Asynchronous Circuits and Systems, International Symposium on
By Tilman Kolks, Steven Vercauteren, Bill Lin
Issue Date:March 1996
pp. 233
Syntax directed translation based compilation from high-level concurrent programs has matured significantly over the past few years. They have been applied to significant designs in the domains of digital signal processing and microprocessor designs. For d...
 
Background Memory Management for Dynamic Data Structure Intensive Processing Systems
Found in: Computer-Aided Design, International Conference on
By Bill Lin, Gjalt de Jong, Carl Verdonck, Sven Wuytack, Francky Catthoor
Issue Date:November 1995
pp. 0515
Telecommunication network management applications often require application-specific ICs that use large dynamically allocated stored data structures. Currently available hardware synthesis environments typically do not support dynamic data structure concep...
 
Symbolic Hazard-Free Minimization and Encoding of Asynchronous Finite State Machines
Found in: Computer-Aided Design, International Conference on
By Robert M. Fuhrer, Steven M. Nowick, Bill Lin
Issue Date:November 1995
pp. 0604
This paper presents an automated method for the synthesis of multiple-input-change (MIC) asynchronous state machines. Asynchronous state machine design is subtle since, unlike synchronous synthesis, logic must be implemented without hazards, and state code...
 
Externally Hazard-Free Implementations of Asynchronous Circuits
Found in: Design Automation Conference
By Bill Lin, Chantal Ykman-Couvreur, Milton Sawasaki
Issue Date:June 1995
pp. 718-724
We present a new sum-of-product based asynchronous architecture, called the N-SHOT architecture, that operates correctly under internal hazardous responses and guarantees hazard-freeness at the observable non-input signals. We formally prove that within th...
 
Hierarchical Optimization of Asynchronous Circuits
Found in: Design Automation Conference
By Tilman Kolks, Gjalt de Jong, Bill Lin
Issue Date:June 1995
pp. 712-717
Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and communicate with each other. This paper is concerned with the problem of synthesizing such...
 
LEISURE: Load-Balanced Network-Wide Traffic Measurement and Monitor Placement
Found in: IEEE Transactions on Parallel and Distributed Systems
By Chia-Wei Chang,Guanyao Huang,Bill Lin,Chen-Nee Chuah
Issue Date:November 2013
pp. 1
Network-wide traffic measurement is of interest to network operators to uncover global network behavior for the management tasks. Increasingly, they are requiring in-depth fine-grained flow-level measurements. However, performing in-depth per-flow measurem...
 
Resistive Computation: A Critique
Found in: IEEE Computer Architecture Letters
By Hamid Mahmoodi,Sridevi Lakshmipuram,Manish Arora,Yashar Asgarieh,Houman Homayoun,Bill Lin,Dean M. Tullsen
Issue Date:August 2013
pp. 1
Resistive Computation [6] replaces conventional CMOS logic with Magnetic Tunnel Junction (MTJ) based Look-Up Tables (LUTs). It has been proposed for tackling the power wall. Spin Transfer Torque RAM (STTRAM) is an emerging CMOS compatible non-volatile memo...
 
Per-Flow Queue Management with Succinct Priority Indexing Structures for High Speed Packet Scheduling
Found in: IEEE Transactions on Parallel and Distributed Systems
By Hao Wang,Bill Lin
Issue Date:July 2013
pp. 1380-1389
Priority queues are essential building blocks for implementing advanced per-flow service disciplines and hierarchical quality-of-service at high-speed network links. Scalable priority queue implementation requires solutions to two fundamental problems. The...
 
LEISURE: A Framework for Load-Balanced Network-Wide Traffic Measurement
Found in: Symposium On Architecture For Networking And Communications Systems
By Chia-Wei Chang,Guanyao Huang,Bill Lin,Chen-Nee Chuah
Issue Date:October 2011
pp. 250-260
Network-wide traffic measurement is of interest to network operators to uncover global network behavior for the management tasks of traffic accounting, debugging or troubleshooting, security, and traffic engineering. Increasingly, sophisticated network mea...
 
Destination-based congestion awareness for adaptive routing in 2D mesh networks
Found in: ACM Transactions on Design Automation of Electronic Systems (TODAES)
By Bill Lin, Rohit Sunkam Ramanujam
Issue Date:October 2013
pp. 1-27
The choice of routing algorithm plays a vital role in the performance of on-chip interconnection networks. Adaptive routing is appealing because it offers better latency and throughput than oblivious routing, especially under nonuniform and bursty traffic....
     
An on-chip global broadcast network design with equalized transmission lines in the 1024-core era
Found in: Proceedings of the International Workshop on System Level Interconnect Prediction (SLIP '12)
By Bill Lin, Chung-Kuan Cheng, Guang Sun, Lieguang Zeng, Shih-Hung Weng
Issue Date:June 2012
pp. 11-18
Based on current trends in multicore scaling, chips with 1024 cores may be available within the next decade. For such number of cores, cache coherence becomes a critical challenge because of the broadcasting operation. For the conventional electrical mesh ...
     
A novel 3D layer-multiplexed on-chip network
Found in: Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS '09)
By Bill Lin, Rohit Sunkam Ramanujam
Issue Date:October 2010
pp. 123-132
Recently, a near-optimal oblivious routing algorithm for 3D mesh networks called Randomized Partially-Minimal (RPM) routing was proposed [12], which works by load-balancing traffic across vertical layers and routing minimally on each horizontal layer. It a...
     
Weighted random oblivious routing on torus networks
Found in: Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS '09)
By Bill Lin, Rohit Sunkam Ramanujam
Issue Date:October 2010
pp. 104-112
Torus, mesh, and flattened butterfly networks have all been considered as candidate architectures for on-chip interconnection networks. In this paper, we study the problem of optimal oblivious routing for one of these architecture classes, namely, the toru...
     
Design and performance analysis of a DRAM-based statistics counter array architecture
Found in: Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS '09)
By Bill Lin, Haiquan (Chuck) Zhao, Hao Wang, Jun (Jim) Xu
Issue Date:October 2010
pp. 84-93
The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable research attention in recent years. This problem arises in a variety of router ...
     
A block-based reservation architecture for the implementation of large packet buffers
Found in: Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS '09)
By Bill Lin, Hao Wang
Issue Date:October 2010
pp. 64-65
DRAM is typically needed to implement large packet buffers, but DRAM devices have worst-case random access latencies that are too slow to match the bandwidth requirements of high-performance routers. Existing DRAM-based architectures for supporting linespe...
     
Destination-based adaptive routing on 2D mesh networks
Found in: Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS '10)
By Bill Lin, Rohit Sunkam Ramanujam
Issue Date:October 2010
pp. 1-12
The choice of routing algorithm plays a vital role in the performance of on-chip interconnection networks. Adaptive routing is appealing because it offers better latency and throughput than oblivious routing, especially under non-uniform and bursty traffic...
     
Trace-driven optimization of networks-on-chip configurations
Found in: Proceedings of the 47th Design Automation Conference (DAC '10)
By Andrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Sunkam Ramanujam
Issue Date:June 2010
pp. 437-442
Networks-on-chip (NoCs) are becoming increasingly important in general-purpose and application-specific multi-core designs. Although uniform router configurations are appropriate for general-purpose NoCs, router configurations for application-specific NoCs...
     
BRICK: a novel exact active statistics counter architecture
Found in: Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS '08)
By Bill Lin, Haiquan (Chuck) Zhao, Jun (Jim) Xu, Nan Hua
Issue Date:November 2008
pp. 77-81
In this paper, we present an exact active statistics counter architecture called BRICK (Bucketized Rank Indexed Counters) that can efficiently store per-flow variable-width statistics counters entirely in SRAM while supporting both fast updates and lookups...
     
Frame-aggregated concurrent matching switch
Found in: Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems (ANCS '07)
By Bill Lin
Issue Date:December 2007
pp. 107-116
Network operators need high-capacity router architectures that can offer scalability, provide throughput and performance guarantees, and maintain packet ordering. However, previous router architectures based on centralized crossbar-based architectures cann...
     
Minimizing collateral damage by proactive surge protection
Found in: Proceedings of the 2007 workshop on Large scale attack defense (LSAD '07)
By Bill Lin, Jerry Chou, Oliver Spatscheck, Subhabrata Sen
Issue Date:August 2007
pp. 63-70
Existing mechanisms for defending against distributed denial-of-service (DDoS) attacks are generally reactive in nature. However, the onset of large-scale bandwidth-based attacks can occur suddenly, potentially knocking out substantial parts of a network b...
     
Stream execution on wide-issue clustered VLIW architectures
Found in: Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools (LCTES '07)
By Bill Lin, Shan Yan
Issue Date:June 2007
pp. 158-160
This paper investigates the mapping of stream programs to wide-issue clustered VLIW processors so that designers can leverage their existing investments in VLIW-based platforms to harness the advantages of stream programming.
     
Hardware compilation for FPGA-based configurable computing machines
Found in: Proceedings of the 36th ACM/IEEE conference on Design automation conference (DAC '99)
By Bill Lin, Xiaohan Zhu
Issue Date:June 1999
pp. 697-702
Due to a patent dispute, full text of this article is not availableat this time.
     
Software synthesis of process-based concurrent programs
Found in: Proceedings of the 35th annual conference on Design automation conference (DAC '98)
By Bill Lin
Issue Date:June 1998
pp. 502-505
We present a Petri net theoretic approach to the software synthesis problem that can synthesize ordinary C programs from process-based concurrent specifications without the need for a run-time multi-threading environment. The synthesized C programs can be ...
     
A strategy for real-time kernel support in application-specific HW/SW embedded architectures
Found in: Proceedings of the 33rd annual conference on Design automation conference (DAC '96)
By Bill Lin, Hugo De Man, Steven Vercauteren
Issue Date:June 1996
pp. 678-683
A new gridless router accelerated by Content Addressable Memory (CAM) is presented. A gridless version of the line-expansion algorithm is implemented, which always finds a path if one exists. The router runs in linear time by means of the CAM-based acceler...
     
A system design methodology for software/hardware co-development of telecommunication network applications
Found in: Proceedings of the 33rd annual conference on Design automation conference (DAC '96)
By Bill Lin
Issue Date:June 1996
pp. 672-677
A new gridless router accelerated by Content Addressable Memory (CAM) is presented. A gridless version of the line-expansion algorithm is implemented, which always finds a path if one exists. The router runs in linear time by means of the CAM-based acceler...
     
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