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Displaying 1-5 out of 5 total
Performance and power efficient on-chip communication using adaptive virtual point-to-point connections
Found in: Networks-on-Chip, International Symposium on
By Mehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol
Issue Date:May 2009
pp. 203-212
In this paper, we propose a packet-switched network-on-chip (NoC) architecture which can provide a number of low-power, low-latency virtual point-to-point connections for communication flows. The work aims to improve the power and performance metrics of pa...
Mesh Connected Crossbars: A Novel NoC Topology with Scalable Communication Bandwidth
Found in: Parallel and Distributed Processing with Applications, International Symposium on
By Arash Tavakkol, Reza Moraveji, Hamid Sarbazi-Azad
Issue Date:December 2008
pp. 319-326
Recent studies have revealed that on-chip interconnects neither is wire plentiful nor is bandwidth cheap. Based on the results of these studies, in physical design of Multiprocessor System-on-Chip (MPSoCs), both the wiring density constraint and routing of...
Virtual Point-to-Point Links in Packet-Switched NoCs
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Mehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol
Issue Date:April 2008
pp. 433-436
A method to setup virtual point-to-point links between the cores of a packet-switched network-on-chip is presented in this paper which aims at reducing the NoC power consumption and delay. The router architecture proposed in this paper provides packet-swit...
An Adaptive Software-Based Deadlock Recovery Technique
Found in: Advanced Information Networking and Applications Workshops, International Conference on
By Mohammad Mirza-Aghatabar, Arash Tavakkol, Hamid Sarbazi-Azad, Abbas Nayebi
Issue Date:March 2008
pp. 514-519
Deadlock management has a direct effect on making a reliable connection between processing nodes in parallel computers. Networks using wormhole switching are the most vulnerable networks to deadlock occurrence due to chained blocking nature of this switchi...
An efficient dynamically reconfigurable on-chip network architecture
Found in: Proceedings of the 47th Design Automation Conference (DAC '10)
By Arash Tavakkol, Hamid Sarbazi-Azad, Mehdi Modarressi
Issue Date:June 2010
pp. 166-169
In this paper, we present a reconfigurable architecture for NoCs on which arbitrary application-specific topologies can be implemented. The proposed NoC can dynamically tailor its topology to the traffic pattern of different applications at run-time. The r...