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Displaying 1-39 out of 39 total
Energy-Aware Computing
Found in: IEEE Micro
By Thomas F. Wenisch,Alper Buyuktosunoglu
Issue Date:September 2012
pp. 6-8
The introduction to the special issue discusses efforts in the area of energy-aware computing.
   
Long-Term Workload Phases: Duration Predictions and Applications to DVFS
Found in: IEEE Micro
By Canturk Isci, Alper Buyuktosunoglu, Margaret Martonosi
Issue Date:September 2005
pp. 39-51
Computer systems increasingly rely on adaptive dynamic management of their operations to balance power and performance goals. Such dynamic adjustments rely heavily on the system's ability to observe and predict workload behavior and system responses. The a...
 
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Greg Semeraro, Grigorios Magklis, Michael L. Scott
Issue Date:September 2002
pp. 141
Energy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be realized for adaptive storage structures such as caches, issue queues, and register files by disabling unnecessary storage resources. Prior studies ha...
 
SMT Switch: Software Mechanisms for Power Shifting
Found in: IEEE Computer Architecture Letters
By Priyanka Tembey,Augusto Vega,Alper Buyuktosunoglu,Dilma Da Silva,Pradip Bose
Issue Date:July 2013
pp. 67-70
Simultaneous multithreading (SMT) as a processor design to achieve higher levels of system and application throughput is a well-accepted and deployed technique in most desktop and server processors. We study the power implications of varying SMT levels i.e...
 
Runtime Application Behavior Prediction Using a Statistical Metric Model
Found in: IEEE Transactions on Computers
By Ruhi Sarikaya,Canturk Isci,Alper Buyuktosunoglu
Issue Date:March 2013
pp. 575-588
Adaptive computing systems rely on accurate predictions of application behavior to understand and respond to the dynamically varying characteristics. In this study, we present a Statistical Metric Model (SMM) that is system- and metric-independent for pred...
 
Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks
Found in: 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
By Ramon Bertran,Alper Buyuktosunoglu,Meeta S. Gupta,Marc Gonzalez,Pradip Bose
Issue Date:December 2012
pp. 199-211
Microprocessor-based systems today are composed of multi-core, multi-threaded processors with complex cache hierarchies and gigabytes of main memory. Accurate characterization of such a system, through predictive pre-silicon modeling and/or diagnostic post...
 
Accurate Fine-Grained Processor Power Proxies
Found in: 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
By Wei Huang,Charles Lefurgy,William Kuk,Alper Buyuktosunoglu,Michael Floyd,Karthick Rajamani,Malcolm Allen-Ware,Bishop Brock
Issue Date:December 2012
pp. 224-234
There are not yet practical and accurate ways to directly measure core power in a microprocessor. This limits the granularity of measurement and control for computer power management. We overcome this limitation by presenting an accurate runtime per-core p...
 
Architectural perspectives of future wireless base stations based on the IBM PowerENâ„¢ processor
Found in: High-Performance Computer Architecture, International Symposium on
By Augusto Vega,Pradip Bose,Alper Buyuktosunoglu,Jeff Derby,Michele Franceschini,Charles Johnson,Robert Montoye
Issue Date:February 2012
pp. 1-10
In wireless networks, base stations are responsible for operating on large amounts of traffic at high speed rates. With the advent of new standards, as 4G, further pressure is put in the hardware requirements to satisfy speeds of up to 1 Gbps. In this work...
 
CPU Accounting for Multicore Processors
Found in: IEEE Transactions on Computers
By Carlos Luque,Miquel Moreto,Francisco J. Cazorla,Roberto Gioiosa,Alper Buyuktosunoglu,Mateo Valero
Issue Date:February 2012
pp. 251-264
In single-threaded processors and Symmetric Multiprocessors the execution time of a task depends on the other tasks it runs with (the workload), since the Operating System (OS) time shares the CPU(s) between tasks in the workload. However, the time account...
 
Energy-Aware Accounting and Billing in Large-Scale Computing Facilities
Found in: IEEE Micro
By Victor Jimenez, Roberto Gioiosa, Francisco J. Cazorla, Mateo Valero, Eren Kursun, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose
Issue Date:May 2011
pp. 60-71
<p>Proposals have focused on reducing energy requirements for large-scale computing facilities (LSCFs), but little research has addressed the need for energy-usage-based accounting. Energy-aware accounting and billing benefits LSCF owners and users. ...
 
Introducing the Adaptive Energy Management Features of the Power7 Chip
Found in: IEEE Micro
By Michael Floyd, Malcolm Allen-Ware, Karthick Rajamani, Bishop Brock, Charles Lefurgy, Alan J. Drake, Lorena Pesantez, Tilman Gloekler, Jose A. Tierno, Pradip Bose, Alper Buyuktosunoglu
Issue Date:March 2011
pp. 60-75
<p>Power7 implements several new adaptive power management techniques which, in concert with the EnergyScale firmware, let it proactively exploit variations in workload, environmental conditions, and overall system use to meet customer-directed power...
 
Abstraction and microarchitecture scaling in early-stage power modeling
Found in: High-Performance Computer Architecture, International Symposium on
By Hans Jacobson, Alper Buyuktosunoglu, Pradip Bose, Emrah Acar, Richard Eickemeyer
Issue Date:February 2011
pp. 394-405
Early-stage, microarchitecture-level power modeling methodologies have been used in industry and academic research for a decade (or more). Such methods use cycle-accurate performance simulators and deduce active power based on utilization markers. A key qu...
 
A case for guarded power gating for multi-core processors
Found in: High-Performance Computer Architecture, International Symposium on
By Niti Madan, Alper Buyuktosunoglu, Pradip Bose, Murali Annavaram
Issue Date:February 2011
pp. 291-300
Dynamic power management has become an essential part of multi-core processors and associated systems. Dedicated controllers with embedded power management firmware are now an integral part of design in such multi-core server systems. Devising a robust pow...
 
ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Carlos Luque, Miquel Moreto, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero
Issue Date:September 2009
pp. 203-213
Chip-MultiProcessor (CMP) architectures are becoming more and more popular as an alternative to the traditional processors that only extract instruction-level parallelism from an application. CMPs introduce complexities when accounting CPU utilization. Thi...
 
Dynamic power gating with quality guarantees
Found in: Low Power Electronics and Design, International Symposium on
By Anita Lungu, Pradip Bose, Alper Buyuktosunoglu, Daniel J. Sorin
Issue Date:August 2009
pp. 377-382
Power gating is usually driven by a predictive control, and frequent mispredictions can counter-productively lead to a large increase in energy consumption. This energy vulnerability could be exploited by malicious applications such as a power virus, or it...
 
A Unified Prediction Method for Predicting Program Behavior
Found in: IEEE Transactions on Computers
By Ruhi Sarikaya, Alper Buyuktosunoglu
Issue Date:February 2010
pp. 272-282
Dynamic management of computer resources is essential for adaptive computing. Adaptive computing systems rely on accurate and robust metric predictors to exploit runtime behavior of programs. In this study, we propose the Unified Prediction Method (UPM) th...
 
CPU Accounting in CMP Processors
Found in: IEEE Computer Architecture Letters
By Carlos Luque, Miquel Moreto, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero
Issue Date:January 2009
pp. 17-20
Chip-Multiprocessor (CMP) architectures introduce complexities when accounting CPU utilization to processes because the progress done by a process during an interval of time highly depends on the activity of the other processes it is co-scheduled with. In ...
 
Software-Controlled Priority Characterization of POWER5 Processor
Found in: Computer Architecture, International Symposium on
By Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, Mateo Valero
Issue Date:June 2008
pp. 415-426
Due to the limitations of instruction-level parallelism, thread-level parallelism has become a popular way to improve processor performance. One example is the IBM POWER5TM processor, a two-context simultaneous-multithreaded dual-core chip. In each SMT cor...
 
Predicting Program Behavior Based On Objective Function Minimization
Found in: IEEE Workload Characterization Symposium
By Ruhi Sarikaya, Alper Buyuktosunoglu
Issue Date:September 2007
pp. 25-34
Computer systems increasingly rely on dynamic management of their operations with the goal of optimizing an individual or joint metric involving performance, power, temperature, reliability and so on. Such an adaptive system requires an accurate, reliable,...
 
Evaluating design tradeoffs in on-chip power management for CMPs
Found in: Low Power Electronics and Design, International Symposium on
By Joseph Sharkey, Alper Buyuktosunoglu, Pradip Bose
Issue Date:August 2007
pp. 44-49
In light of the recent shift towards multi-core processor designs, dynamic power-management techniques that were designed for single-core microprocessors must be augmented with larger chip-level control. In this paper, we explore the design-tradeoffs assoc...
 
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Canturk Isci, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose, Margaret Martonosi
Issue Date:December 2006
pp. 347-358
Chip-level power and thermal implications will continue to rule as one of the primary design constraints and performance limiters. The gap between average and peak power actually widens with increased levels of core integration. As such, if per-core contro...
 
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors
Found in: High-Performance Computer Architecture, International Symposium on
By Hans Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor Zyuban, Rick Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel Tendler
Issue Date:February 2005
pp. 238-242
Clock-gating has been introduced as the primary means of dynamic power management in recent high-end commercial microprocessors. The temperature drop resulting from active power reduction can result in additional leakage power savings in future processors....
 
Microarchitectural Techniques for Power Gating of Execution Units
Found in: Low Power Electronics and Design, International Symposium on
By Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor Zyuban, Hans Jacobson, Pradip Bose
Issue Date:August 2004
pp. 32-37
Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-gating of execution units. This paper first develops parameterized analytical...
 
Dynamically Tuning Processor Resources with Adaptive Processing
Found in: Computer
By David H. Albonesi, Rajeev Balasubramonian, Steven G. Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley E. Schuster
Issue Date:December 2003
pp. 49-58
<p>The <em>adaptive processing approach</em> improves microprocessor energy efficiency by dynamically tuning major resources during execution to better match varying application needs. This tuning usually involves reducing a resource's si...
 
A Dynamically Tunable Memory Hierarchy
Found in: IEEE Transactions on Computers
By Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
Issue Date:October 2003
pp. 1243-1258
<p><b>Abstract</b>—The widespread use of repeaters in long wires creates the possibility of dynamically sizing regular on-chip structures. We present a tunable cache and translation lookaside buffer (TLB) hierarchy that leverages repeater...
 
Energy Efficient Co-Adaptive Instruction Fetch and Issue
Found in: Computer Architecture, International Symposium on
By Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose
Issue Date:June 2003
pp. 147
Front-end instruction delivery accounts for a significant fraction of the energy consumed in a dynamic superscalar processor. The issue queue in these processors serves two crucial roles: it bridges the front and back ends of the processor and serves as th...
 
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors
Found in: IEEE Micro
By David M. Brooks, Pradip Bose, Stanley E. Schuster, Hans Jacobson, Prabhakar N. Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor Zyuban, Manish Gupta, Peter W. Cook
Issue Date:November 2000
pp. 26-44
Power dissipation limits have emerged as a major constraint in the design of microprocessors. This is true not only at the low end, where cost and battery life are the primary drivers, but also now at the midrange and high-end system (server) level. Thus, ...
 
Comparing Implementations of Near-Data Computing with In-Memory MapReduce Workloads
Found in: IEEE Micro
By Seth H. Pugsley,Jeffrey Jestes,Rajeev Balasubramonian,Vijayalakshmi Srinivasan,Alper Buyuktosunoglu,Al Davis,Feifei Li
Issue Date:July 2014
pp. 44-52
The emergence of 3D stacking and the imminent release of Micron's Hybrid Memory Cube (HMC) device have made it more practical to move computation near memory. This work presents a detailed analysis of in-memory MapReduce in the context of near-data computi...
 
NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads
Found in: 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
By Seth H Pugsley,Jeffrey Jestes,Huihui Zhang,Rajeev Balasubramonian,Vijayalakshmi Srinivasan,Alper Buyuktosunoglu,Al Davis,Feifei Li
Issue Date:March 2014
pp. 190-200
While Processing-in-Memory has been investigated for decades, it has not been embraced commercially. A number of emerging technologies have renewed interest in this topic. In particular, the emergence of 3D stacking and the imminent release of Micron's Hyb...
   
3D stacking of high-performance processors
Found in: 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
By Philip Emma,Alper Buyuktosunoglu,Michael Healy,Krishnan Kailas,Valentin Puente,Roy Yu,Allan Hartstein,Pradip Bose,Jaime Moreno
Issue Date:February 2014
pp. 500-511
In most 3D work to date, people have looked at two situations: 1) a case in which power density is not a problem, and the parts of a processor and/or entire processors can be stacked atop each other, and 2) a case in which power density is limited, and sto...
   
SMT-centric power-aware thread placement in chip multiprocessors
Found in: 2013 22nd International Conference on Parallel Architectures and Compilation Techniques (PACT)
By Augusto Vega,Alper Buyuktosunoglu,Pradip Bose
Issue Date:September 2013
pp. 167-176
In Simultaneous Multi-Threading (SMT) chip multiprocessors (CMPs), thread placement is performed today in a largely power-unaware manner. For example, consolidation of active threads into fewer cores exposes opportunities for power savings that have not be...
   
Crank it up or dial it down: coordinated multiprocessor frequency and folding control
Found in: Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46)
By Pradip Bose, Srinivasan Ramani, Alper Buyuktosunoglu, Augusto Vega, Heather Hanson
Issue Date:December 2013
pp. 210-221
Dynamic power management features are now an integral part of processor chip and system design. Dynamic voltage and frequency scaling (DVFS), core folding and per-core power gating (PCPG) are power control actuators (or "knobs") that are available in moder...
     
Making data prefetch smarter: adaptive prefetching on POWER7
Found in: Proceedings of the 21st international conference on Parallel architectures and compilation techniques (PACT '12)
By Alper Buyuktosunoglu, Francis P. O'Connell, Francisco J. Cazorla, Pradip Bose, Roberto Gioiosa, Victor Jiménez
Issue Date:September 2012
pp. 137-146
Hardware data prefetch engines are integral parts of many general purpose server-class microprocessors in the field today. Some prefetch engines allow the user to change some of their parameters. The prefetcher, however, is usually enabled in a default con...
     
Dynamic power gating with quality guarantees
Found in: Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design (ISLPED '09)
By Alper Buyuktosunoglu, Anita Lungu, Daniel J. Sorin, Pradip Bose
Issue Date:August 2009
pp. 1-2
Power gating is usually driven by a predictive control, and frequent mispredictions can counter-productively lead to a large increase in energy consumption. This energy vulnerability could be exploited by malicious applications such as a power virus, or it...
     
Evaluating design tradeoffs in on-chip power management for CMPs
Found in: Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)
By Alper Buyuktosunoglu, Joseph Sharkey, Pradip Bose
Issue Date:August 2007
pp. 44-49
In light of the recent shift towards multi-core processor designs, dynamic power-management techniques that were designed for single-core microprocessors must be augmented with larger chip-level control. In this paper, we explore the design-tradeoffs assoc...
     
Microarchitectural techniques for power gating of execution units
Found in: Proceedings of the 2004 international symposium on Low power electronics and design (ISLPED '04)
By Alper Buyuktosunoglu, Hans Jacobson, Pradip Bose, Victor Zyuban, Viji Srinivasan, Zhigang Hu
Issue Date:August 2004
pp. 32-37
Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-gating of execution units. This paper first develops parameterized analytical...
     
Tradeoffs in power-efficient issue queue design
Found in: Proceedings of the 2002 international symposium on Low power electronics and design (ISLPED '02)
By Alper Buyuktosunoglu, David H. Albonesi, Peter W. Cook, Pradip Bose, Stanley E. Schuster
Issue Date:August 2002
pp. 184-189
A major consumer of microprocessor power is the issue queue. Several microprocessors, including the Alpha 21264 and POWER4TM, use a compacting latch-based issue queue design which has the advantage of simplicity of design and verification. The disadvantage...
     
A circuit level implementation of an adaptive issue queue for power-aware microprocessors
Found in: Proceedings of the 11th Great Lakes Symposium on VLSI (GLSVLSI '01)
By Alper Buyuktosunoglu, David Albonesi, David Brooks, Peter Cook, Pradip Bose, Stanley Schuster
Issue Date:March 2001
pp. 73-78
The concept of a “transparent repeater1,” which is an amplifier circuit designed to minimize the delay introduced by highly resistive interconnect lines in high speed digital circuits, is introduced and described in this paper. An insertion met...
     
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
Found in: Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture (MICRO 33)
By Alper Buyuktosunoglu, David Albonesi, Rajeev Balasubramonian, Sandhya Dwarkadas
Issue Date:December 2000
pp. 245-257
Recent research has suggested that the branch history register need not contain the outcomes of the most recent branches in order for the Two-Level Adaptive Branch Predictor to work well. From this result, it is tempting to conclude that the branch history...
     
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